STA_L1d - Importance of Timing From RTL to Logic Synthesis

To understand the importance of STA, it's very important to know VLSI Design flow and how different timing checks are required at different stages.
In previous video:
STA_L1a: I have discussed generic VLSI Design Flow. (Link of previous video : • STA_L1a - Overview of ... )
STA_L1b: I have discussed generic Overview of VLSI Frontend Design Flow. (Link of previous video : • STA_L1b - Overview of ... )
STA_L1c: I have discussed generic Overview of VLSI Backend Design Flow. (Link of previous video : • STA_L1c Overview of VL... )
In this part - I have captured the importance of Timing Analysis From RTL to Logic Synthesis.

[@rizeenshaikh73]

sir i am completely new to the timing violations i am not understanding the paths in vivado from where to where there is the path and which codes inthat path i should check, can u please guide me with the vivado tool.

[@vlsiexpert]

You can understand yourself - once you go through the Timing Path sessions

[@rizeenshaikh73]

@@vlsiexpert where wil i get this "Timing Path sessions" ?