Omg I never knew this formula has a proof also... LPU was blessed to have u sir ... Bad luck that I never got the opportunity to learn from u physically.
One unique thing about every Gate Smashers lecture that I have cherished since my Btech days: All videos always have: -> Explanation of prior concept required to understand this one - Provides context. -> Explanation of need of this particular concept - Provides motivation. -> Explanation of how the need is satisfied with the current concept - Provides insight. Salute to you sir. Thank you for your selfless contribution towards the Indian CS Engineering scene overall.
sir, digital electronics mein problem hota hein competitive exam point of view se. f/f, counters agar questions leke solving procedure discuss kar date bohut help ho jata...
Sir! I loved your work. Simple clear and effective. Efforts you put in your videos is tremendous. Hope you read this and smile. I wish you more success and good health. Peace be upon you.🤍
🎯 Key Takeaways for quick navigation: 00:00 Virtual *memory provides an illusion that processes larger than main memory can be executed, overcoming the limitation of finite main memory sizes.* 02:26 Virtual *memory divides processes into pages, bringing only required pages into main memory based on the concept of locality of reference.* 05:37 Swap-in *and swap-out operations, or roll-in and roll-out, manage bringing pages into main memory and replacing them when needed.* 06:36 Virtual *memory allows executing processes without limitations on their size or number, despite the constraints of limited main memory.* 07:29 Page *faults occur when a CPU demands a page not present in main memory, leading to a brief interruption in control and a switch to the operating system.* 12:38 Page *fault service involves searching for the required page in logical address space, bringing it from the hard disk to main memory, and updating the page table.* 14:29 Effective *memory access time is calculated as P times page fault service time plus 1-P times main memory access time, highlighting the impact of page faults on overall performance.* 19:12 Excessive *page faults can lead to threshing, causing degradation in CPU utilization and overall system performance.* Made with HARPA AI
please help me with my confusion : when a miss occurs first it checks the TLB then it goes for Page table, and finally to the main memory --> so why not the effective memory access time is: TLB + Page Table Time(x) + Page Access time (x) = TLB + x + x? but it is actually ( TLB + x) + (TLB + x + x) --> even when we are accessing the TLB just one and shifting to page table? Sir, said both combined is the total time for a miss, but i think its just (TLB + x + x). Thank you in advance for any assistance you can provide.
Hi Sir, One Doubt, For the miss case, why the EMAT will have X in (TLB + X)? If it was a hit then X will be the time taken to find the frame in Main Memory, but if in TLBitself fail then it will reach to page table below the TLB right? So EMAT = (TLB) +(TLB+X) ??
Sir please upload some videos about VIPT, PIPT, VIVT caches. I have tried to refer to some resources but I’m falling in lot of confusions. Please upload a video regarding these topics. It would be really helpful🙏
small correction : Effective memory access time is given as h*(c+m) + (1-h)*(c+2m) where h-> hit ratio of TLB. C-> TLB access time m -> memory access time. Great lecture btw.
at 10:27 in case of tlb miss as you have written there EMAT=(TLB+x (but if its tlb miss then we didnt access the MM then we dont need to add x for tlb misss) )+Miss(TLB+x+x) so may be it will be like EMAT=TLB+Miss(TLB+x+x) isnt it?
I have a doubt if anyone could clear,to find the page table do we search the main memory page by page? If yes then how accesing a page table time and accesing the frame of that particular process is same? Because page table will give us the physical address of the particular page we are finding and we directly go to that address but for page table we have to search it.
Consider a paging system that uses 1-level page table residing in main memory and a TLB for address translation. Each main memory access takes 100 ns and TLB lookup takes 20 ns. Each page transfer to/from the disk takes 5000 ns. Assume that the TLB hit ratio is 95%, page fault rate is 10%. Assume that for 20% of the total page faults, a dirty page has to be written back to disk before the required page is read from disk. TLB update time is negligible. The average memory access time in ns (round off to 1 decimal places) is Sir pls explain
![The Wall Song ร้องข้ามกำแพง | EP.215 | พาเวล นเรศ - พูห์ กฤติน | 17 ต.ค. 67 [1/5]](http://i.ytimg.com/vi/IUzrjuf60P4/mqdefault.jpg)
Thank you for uploading this series for free.
Sir ur teaching style so simple that everyone can understand without any doubt
WOW... You have explained this concept very nicely sir ... Thank you so much !!!
Omg I never knew this formula has a proof also... LPU was blessed to have u sir ... Bad luck that I never got the opportunity to learn from u physically.
My prof just posted slides due to coronavirus , thanks to you i can understand the concepts now
One unique thing about every Gate Smashers lecture that I have cherished since my Btech days:
All videos always have:
-> Explanation of prior concept required to understand this one - Provides context.
-> Explanation of need of this particular concept - Provides motivation.
-> Explanation of how the need is satisfied with the current concept - Provides insight.
Salute to you sir. Thank you for your selfless contribution towards the Indian CS Engineering scene overall.
Sir ji, Thank you so much. You are the only reason I'm gonna pass my exam.
Thank you Sir. I used to hate this subject but it has become very easy for me only because of your videos
sir, digital electronics mein problem hota hein competitive exam point of view se. f/f, counters agar questions leke solving procedure discuss kar date bohut help ho jata...
Crystal clear explaination cleared my doubt of tlb !! thank u sir
Thank you sir for uploading this video. Mujhe laga aap itne important topic kaise chor sakte hain.
very beautifully explained how the formula is generated..... understood for the first time how this formula is generated. Thanks!
TLB starts at 5:40
Sir! I loved your work. Simple clear and effective. Efforts you put in your videos is tremendous. Hope you read this and smile. I wish you more success and good health.
Peace be upon you.🤍
Really a good way of teaching.. it's simple and understandable.. thank you..
nice sir aap apna 100% DE RAHE HO
Very simple person with beautiful explainatipn
I always like ur video. My request to everyne .pls like his videos . Like hit se trp badti hai bhai...
After watching your video interest jaag jata hai subject par
Kya baat bai ji. Thank you for your clear and concise explanation!
Also, In TLB miss occur the TLB is updated with page number and frame number so in future if same page is accessed no need to go the page table.😊
Tq
🎯 Key Takeaways for quick navigation:
00:00 Virtual *memory provides an illusion that processes larger than main memory can be executed, overcoming the limitation of finite main memory sizes.*
02:26 Virtual *memory divides processes into pages, bringing only required pages into main memory based on the concept of locality of reference.*
05:37 Swap-in *and swap-out operations, or roll-in and roll-out, manage bringing pages into main memory and replacing them when needed.*
06:36 Virtual *memory allows executing processes without limitations on their size or number, despite the constraints of limited main memory.*
07:29 Page *faults occur when a CPU demands a page not present in main memory, leading to a brief interruption in control and a switch to the operating system.*
12:38 Page *fault service involves searching for the required page in logical address space, bringing it from the hard disk to main memory, and updating the page table.*
14:29 Effective *memory access time is calculated as P times page fault service time plus 1-P times main memory access time, highlighting the impact of page faults on overall performance.*
19:12 Excessive *page faults can lead to threshing, causing degradation in CPU utilization and overall system performance.*
Made with HARPA AI
lol 19 minute ka time tag kiska dera hai ye ai
Great explanation, Thank you sir
I have got a clear understanding of this concept..thanks for your videos
please help me with my confusion :
when a miss occurs
first it checks the TLB then it goes for Page table, and finally to the main memory --> so why not the effective memory access time is: TLB + Page Table Time(x) + Page Access time (x) = TLB + x + x?
but it is actually
( TLB + x) + (TLB + x + x) --> even when we are accessing the TLB just one and shifting to page table? Sir, said both combined is the total time for a miss, but i think its just (TLB + x + x). Thank you in advance for any assistance you can provide.
Very well explained...thank you Sir✌️
You are the best in explaining the concept if it was in English subtitles it would have been better thanks bhai🙏🏼
Your feedback has been heard!
waow sir you are very easily tech now ..
this video es very helpful
Tq broo...nice sweet and short explanation 😊
Thank you. Excellent explanation.
sir your explanation is awesome
Very very very very awesome explanation.
excellent sir......
Great explanation....thank you so much...
Hi Sir, One Doubt,
For the miss case, why the EMAT will have X in (TLB + X)? If it was a hit then X will be the time taken to find the frame in Main Memory, but if in TLBitself fail then it will reach to page table below the TLB right? So EMAT = (TLB) +(TLB+X) ??
perfect delivery sir
best explanation of this buffer : )
Thank you sir
Thank you very much Sir 🌟🙏
Sir please upload some videos about VIPT, PIPT, VIVT caches. I have tried to refer to some resources but I’m falling in lot of confusions. Please upload a video regarding these topics. It would be really helpful🙏
Life saving!!🥵🔥
Sir cpu to page no generate krega to page number se kaise TLB me frame number kr payega?
Kya jo tags h vo page numbers hi h??
Sir har video aap aapka naam lijiye,,
Logo ko pata chalna chahiye kon he ye mahan hasti🙌
Thankyou for your knowledge
Kaafi shi oadhaya hai aapne.
Sir iss TLB ko bhi MMU he use krti hai na?
Page-table cached goes into TLB, part of MMU.
Page cached goes into Primary Cache, sec. Cache
thank u for putting subtitles!
Thanks sir.
Great Video
Sir, essentially TLB is storing page table itself. Aur TLb me nhi toh(Miss condition) toh MM k Page Table me kaise hoga? yeh toh page fault hua na! Please clarify this one.
small correction : Effective memory access time is given as h*(c+m) + (1-h)*(c+2m)
where h-> hit ratio of TLB.
C-> TLB access time
m -> memory access time.
Great lecture btw.
Is this formula correct?
Hey, he wrote hit in the top, he wrote the formula right= h(hit(tlb+x) +(1-h)(tlb+2x)
at 10:27
in case of tlb miss
as you have written there
EMAT=(TLB+x (but if its tlb miss then we didnt access the MM then we dont need to add x for tlb misss) )+Miss(TLB+x+x)
so may be it will be like
EMAT=TLB+Miss(TLB+x+x)
isnt it?
God bless you
Very good explanation ☺️
This was very helpful. Thanks a lot.
Pehle COA me ye concept use hua. Ab 7 months ke baad OS me use ho raha 😂
Superb sir...thanku
can you also explain about software and hardware managed TLB with their advantages and disadvantages?
Just make the video a bit fast I m playing it in 2x 😅😅
BTW nice video!!
But I think the speed is perfect for the slow learners (as if me)
@@kesheep424 aree no worries just chill.
I'm Playing this in 3x LOL 🤣🤣🤣🤣
This lecture is really helpful
In this pandemic, when we are facing difficulties in studies. This man's videos are as effective as the vaccine for virus will be.
efficient memory acces time= h*(c+m)*(1-h)(c+2m) h=hit ratio,c=tlb access time,m=tlb acces time
Superb sir
Thank you sir...
Thank you very much!
Sir virtual memory software hai ya hardware
Sir,
How is it decided that which page number entries go into tlb ?
Really appreciate your videos.
This may be reported by OS
Maza aagya
Sir. Please Make class on multilevel paging ( with how logical address is dividing)
Thanku sir
Thanks alot sir😇😇
Nothing to say just thank you
give a like
from all your fake accounts
What?? I am a student who follow him for my study
@@avijeetgorai3697 i said if you have any other yt accounts give him likes so his channel will grow
Sir pls also provide some notes😇
All videos r good sir please upload in English
Thanks sir❤
crystal clear
Jaha notes bhi provide aap karte ho for computer science students these are preparing for gate exam and isro exam
Cha gye sir
That's very nice
Nice
Good work bro
super '''''''''''''''''''''''''''''''''''''''' Thank YOU
I have a doubt if anyone could clear,to find the page table do we search the main memory page by page? If yes then how accesing a page table time and accesing the frame of that particular process is same? Because page table will give us the physical address of the particular page we are finding and we directly go to that address but for page table we have to search it.
Thanks
Consider a paging system that uses 1-level page table residing in main memory and a TLB for address translation. Each main memory access takes 100 ns and TLB lookup takes 20 ns. Each page transfer to/from the disk takes 5000 ns. Assume that the TLB hit ratio is 95%, page fault rate is 10%. Assume that for 20% of the total page faults, a dirty page has to be written back to disk before the required page is read from disk. TLB update time is negligible.
The average memory access time in ns (round off to 1 decimal places) is
Sir pls explain
nc explanation sir
Sir page fault occurs in the page can't be present in TLB. Is it true or false ? Sir please reply.
Yes
Ok sir thank you.
❤
Thanks sir
v nice
sir make videos on the buffering types
Sir aapka koi telegram channel nahi hai Kya ????
sir, which frames are residing in tlb
jabra fan
👍👍👍
Sir please make test series of gate also
Sir Please Do a Video on BARC CS
Sir plz mark which part among ur videos is in ese sylbs of ece branch....plz sir
Sir Plz make a video on gate 2020 computer organization solution
🙏🙏🙏