Man, I absolutely fucking love your website. The amount of depth you go into simply does not exist anywhere else on the internet, still written in such an enjoyable, easily accessible way. So damn good :) Super excited for more videos! Love how mike clearly very much enjoyed being asked very technical questions for once :D
Great job. I think Mike really enjoyed those in depth questions. Your Interview was a nice contrast to Dr. Ian Cutress` more general overview. Good luck with future videos and interviews!
Great interview! It would be interesting to ask questions like "What is the port sharing algorithm for the register file integer/vector & FP?", "Is the integer execution engine fully bypassed, and what is the bypass scheme?", "Is the unified scheduler doing wake-up and select in a single cycle, and is it still age-ordered?", "What do you mean by 'first wait for ready instruction and then put them in the queues (scheduler)'?" The schedulers, bypass networks, and register file port sharing are some of the hottest topics when it comes to the execution engine. The fact that they seem to have "hidden" the load/store pipes is also interesting. Did they rearchitect them in a fundamentally different way? There are many questions like these that I would love to see interviewers asking guys like Mike.
You sure did the job of Ian (techtechpotato) there😂. Well that coveres the whole Zen 5 architecture. One interesting thing to point is AMD did back to back iterations of zen upto zen 3 in 4 years, Now that zen 5 is new machine, will we see smaller cadence for next generations in upcoming years?
They broke up & rebuilt the architecture of zen again so you can expect Zen 6 or 7 or 8 to be as good as zen 3 was I imagine. Zen 5 is like Zen 1, it won't be significantly better than Zen 4, if barely keep up ( especially in gaming )
Thank you Mr. Cheese for this excelent video. Does anyone know pipeline depth of zen 5 and how many pipeline stages it needs to go back if it mises branch prediction ?
Excuse me but he gave no clue as to what happens when Zen 5 dual predictor & pipelines overlaps the same predictions/instructions for a pull or predict? Can you clarify what exactly would happen inside the core. it's fine in single thread as it would or should just retire the prediction as wrong, before getting to far down. Except when it uses the SMT thread in dual mode it would just be a wasted cycle. Is there some kind of check through the pipeline that they're not an overlay or repeated instruction being predicted? Or is this down by the micro upo cache?
Chop & cheese your test proved the engineer wrong. The dual predictors are not working in single thread at all. Only one predictor & pipeline is being used while running a single thread? Clearly in the transcripte he states that it supposed to be able to use both for a single thread when SMT isn't on, but even with SMT disable it's not using both.
But there are so many more interesting cheeses out there than cheddar 🫠 Great interview! Really interesting hearing the details on resources split with SMT enabled. I'm curious what impact disabling it on client machines will have. It seems like it must add a lot of complexity to the design & validation. Perhaps worth dropping on client products in future?
![[11] Mike Clark, AMD Zen Chief Architect](http://i.ytimg.com/vi/3vyNzgOP5yw/mqdefault.jpg)
![[11] Mike Clark, AMD Zen Chief Architect](/img/tr.png)
Great interview George! Those were great questions! ;)
Mike Clark is class! Love his interview with Dr Cutress aka Potato back when Zen3 was launched (now part of Poutrine)
perfect amount of technicality.
Fantastic interview, great questions - I can’t wait for more in the future :-)
Man, I absolutely fucking love your website. The amount of depth you go into simply does not exist anywhere else on the internet, still written in such an enjoyable, easily accessible way. So damn good :)
Super excited for more videos! Love how mike clearly very much enjoyed being asked very technical questions for once :D
good work dude! loved the questions, I think Zen daddy liked them as well!
Fascinating interview, I could listen to an interview like that for hours.
You have an amazing website and glad that you show yourself in 3D on YT!
Great job. I think Mike really enjoyed those in depth questions. Your Interview was a nice contrast to Dr. Ian Cutress` more general overview. Good luck with future videos and interviews!
Can't wait for more content
No nonsense, just amazing in-depth talk. LOVE IT. Subbed!
Welcome to yt, chips and cheese!
Great interview!
It would be interesting to ask questions like "What is the port sharing algorithm for the register file integer/vector & FP?", "Is the integer execution engine fully bypassed, and what is the bypass scheme?", "Is the unified scheduler doing wake-up and select in a single cycle, and is it still age-ordered?", "What do you mean by 'first wait for ready instruction and then put them in the queues (scheduler)'?"
The schedulers, bypass networks, and register file port sharing are some of the hottest topics when it comes to the execution engine. The fact that they seem to have "hidden" the load/store pipes is also interesting. Did they rearchitect them in a fundamentally different way?
There are many questions like these that I would love to see interviewers asking guys like Mike.
Fantastic interview, thank you!
Thats a great first. 🎉
Great interview! It's really exciting to see you posting a video!
I'm really interested to know when AMD will update the IO die.
great loved your blogs, excited for Chips and Cheese yt journey
Launch of the TH-cam!!!
Great interview!
Mr. Cheese, I love your work
nice gives us some insight on where 10000 is headed
You sure did the job of Ian (techtechpotato) there😂. Well that coveres the whole Zen 5 architecture. One interesting thing to point is AMD did back to back iterations of zen upto zen 3 in 4 years, Now that zen 5 is new machine, will we see smaller cadence for next generations in upcoming years?
They broke up & rebuilt the architecture of zen again so you can expect Zen 6 or 7 or 8 to be as good as zen 3 was I imagine.
Zen 5 is like Zen 1, it won't be significantly better than Zen 4, if barely keep up ( especially in gaming )
Great. really appreciated !!🙂
very very cool, thank you !!!
Thank you Mr. Cheese for this excelent video. Does anyone know pipeline depth of zen 5 and how many pipeline stages it needs to go back if it mises branch prediction ?
great video
Potato sent me
Paging Doctor Ian. Emergency
Excuse me but he gave no clue as to what happens when Zen 5 dual predictor & pipelines overlaps the same predictions/instructions for a pull or predict?
Can you clarify what exactly would happen inside the core. it's fine in single thread as it would or should just retire the prediction as wrong, before getting to far down. Except when it uses the SMT thread in dual mode it would just be a wasted cycle. Is there some kind of check through the pipeline that they're not an overlay or repeated instruction being predicted?
Or is this down by the micro upo cache?
Chop & cheese your test proved the engineer wrong.
The dual predictors are not working in single thread at all. Only one predictor & pipeline is being used while running a single thread?
Clearly in the transcripte he states that it supposed to be able to use both for a single thread when SMT isn't on, but even with SMT disable it's not using both.
gayyyyyyyyyy
But there are so many more interesting cheeses out there than cheddar 🫠
Great interview! Really interesting hearing the details on resources split with SMT enabled. I'm curious what impact disabling it on client machines will have. It seems like it must add a lot of complexity to the design & validation. Perhaps worth dropping on client products in future?
There are so many kinds of cheddar