Associative cache memory

Description of how an associative cache memory works. Some previous knowledge about direct mapped cache is assumed.

[@Zerpentile93]

Came back to watch this again after forgetting this. Thanks so much for the help. The way you explain things is very clear and done in a good order. A lot is common sense though.

[@AbelardoPardo]

Offset is the name used to refer to the number of positions counting from the start of the memory block to access the data in the required address. Since memory block sizes are powers of two, this quantity can be easily obtained by directly taking the value of the least significant bits (how many of them depends on the block size).

[@yatp7216]

Being m the number of bits in the offset and p the block size, we get m = p.
p will be the number of memory addressable units in a single block, memory addressable units can vary from byte, word (2.byte), etc.
Is this correct?

[@raghadamer6445]

Abelardo Pardo how measure the cycle time for cache memory when pipelind design ???? Plz

[@Zerpentile93]

Thank you. Much better than my shitty book.

[@ronylev-ari3219]

your tutorials are just brilliant

[@dassaf5374]

i wish my teacher would have explained it like this! excellent explanation!

[@fit.with_soni]

Awesome! Explaination is purely relevented to the subject " Computer Organisation and Architecture".
Great! Buddy..!!

[@taniahernandez5003]

Thanks for the video! Clear and short :)

[@CodingJesus]

Amazing video, I was reading a whitepaper on caches and this helped clear up a lot of my questions!

[@bryanquintana]

Very helpful!

[@rang20300]

very nice thank you I understand it fully now :)

[@prakashgupta698]

thanks for this wonderful video lecture

[@Princebharti9971]

nicely explained !!

[@rahulcoolify]

Very good explanation.

[@robertfaney4148]

can you please help how to answer this question ?A processor has 30-bit Virtual addresses, 64 Mbyte physical memory organised in 256 Kbyte pages, and a 128 Bytes, 4-way associative TLB with 4 Bytes block size. How big is the Page table? (ignore the status bits) and how many bits are in TLB tag and index?

[@BG0178]

Thank you very much

[@bjar2]

Great videos, well explained concepts. Thank you :)

[@MOHSINALI-bk2qo]

thank you so much..

[@2duniverse]

what is the need of tag comparison in direct associative cache map if we explicitly go to block address ?

[@AbelardoPardo]

Because in a cache block you may several memory blocks. The way to tell them apart is through the tag.

[@rinneplays8403]

I thank you so much for this ..

[@raghadamer6445]

Can anyone help me how measure cycle time for pipelind cashe ?????

[@ankitaojha7438]

but what is a proper definition for associative memory ?

[@keshavgreddyg]

Thank you so much !

[@sohamparikh9315]

Do we not need to include a dirty bit i.e a bit required to represent whether the data has been changed after bringing the block from memory or not?

[@saurabhshah8802]

Depends on the implementation of the cache and coherancy protocols used.

[@snoopy235689]

Thank you so much :)

[@okpeterhu]

Thank you :D

[@user-oc8pu3jp3v]

Thank you so much :)