I recently switched from the MAX V 570Z (TSOP144), same as in the video, to the much superior Lattice MACHO2. For nearly the same price, you get more IO, 9KB of block ram, and hardened I2C and SPI. My performance is nearly 50x greater.
CPLD is Basically Hardware which you can Program however you want. Instead of Using ICs, Gates and Wires just Program it instead. And yes You can Program or Emulate a CPU in CPLD but FPGAs are better for that and few do come along with CPU Cores. Idk BIOS stuff tho
Bill could you please recommend an fpga to begin learning them ? I'm thinking spartan 6 lx16, but usb blaster is expensive. Any other way to flash a xilinx ?
The n parameter is used to denote how many bits is used for the counter register. So, where he has... output reg [n:0] count; When the parameter = 63, the above will actually be "seen" at compile time like this... output reg [63:0] count; This means that the register "count" will have 64 bits total (bit 63 down to bit 0). Bil then chose to route arbitrary bits of the count register directly to the LEDs on the board using the graphical block diagram. The "count" register in this example is clocked at 50MHz, and the count value increments on every rising edge of the main input clock (hence the "posedge" statement in the always block). If you visualize how binary counting works, each bit of the counter toggles half as slow as the first one. So... bit "0" of the count register will toggle at 25MHz. bit "1" of the count register will toggle at 12.5MHz. bit "2" of the count register will toggle at 6.25MHz. ..and so on. You can see that you need quite a few bits to slow down the output signal enough so you can actually see them toggling on the LED(s). ;)
(this may not be 100% correct, but this is to the best of my knowledge)... In the always block, the statements below it will be evaluated every time the terms in the so-called "sensitivity list" are true. The only thing in the sensitivity list in this example is the @(posedge clk). This means that the count = count + 1 part will happen every time we see a rising edge of the clk input. If you have only one statement after the always block, you don't need the "begin" and "end" words. But, if you have more than one thing to evaluate on every rising edge of the clk, you could do this... always @(posedge clk) begin count = count + 1; state = state + 1; end (we don't actually have a "state" register yet, but you get the idea). :)
Marcin Jurczuk btw, from the sort of videos you've watched, and your subs, I'm guessing your question was rhetorical, but thought I'd post some of my ramblings anyway in case somebody else wanted to know. lol
yes, as long as it fits into the C64, and you have an adapter that has the right pins. You'd propably have to use a logic converter, as most modern FPGAs / CPLDs use 3.3v logic, but most older systems (6502, Z80, 8086 etc) used 5v
Thank you, it is great to see the big picture.
Thank you very much you taught me a lot about cplds will help with my projects
I recently switched from the MAX V 570Z (TSOP144), same as in the video, to the much superior Lattice MACHO2. For nearly the same price, you get more IO, 9KB of block ram, and hardened I2C and SPI. My performance is nearly 50x greater.
is there a way to program a standalone CPLD without spending 500€ on a programmer?
How did you loose your finger?
Does a CPLD have its own processor? Does a CPLD operate even before the BIOS/UEFI?
CPLD is Basically Hardware which you can Program however you want. Instead of Using ICs, Gates and Wires just Program it instead. And yes You can Program or Emulate a CPU in CPLD but FPGAs are better for that and few do come along with CPU Cores. Idk BIOS stuff tho
Bill could you please recommend an fpga to begin learning them ? I'm thinking spartan 6 lx16, but usb blaster is expensive. Any other way to flash a xilinx ?
Check this out, it's reaaaaly cheap: www.ebay.com/itm/Altera-FPGA-CPLD-programmer-USB-Blaster-compatible-LC-MAXII-EPM240-Dev-Board/222518023586?hash=item33cf1b95a2%3Am%3AmPES43HZf3xmdUWX-9ACVkA&var=521365773294
What do you think about AMD and Xylinx merging and will AMD Ryzen use FPGA accelerators?
Nice introdution. The only missing thing is basic verilog syntax. And how n parameter translates to blinking time ?
The n parameter is used to denote how many bits is used for the counter register.
So, where he has...
output reg [n:0] count;
When the parameter = 63, the above will actually be "seen" at compile time like this...
output reg [63:0] count;
This means that the register "count" will have 64 bits total (bit 63 down to bit 0).
Bil then chose to route arbitrary bits of the count register directly to the LEDs on the board using the graphical block diagram.
The "count" register in this example is clocked at 50MHz, and the count value increments on every rising edge of the main input clock (hence the "posedge" statement in the always block).
If you visualize how binary counting works, each bit of the counter toggles half as slow as the first one.
So...
bit "0" of the count register will toggle at 25MHz.
bit "1" of the count register will toggle at 12.5MHz.
bit "2" of the count register will toggle at 6.25MHz.
..and so on.
You can see that you need quite a few bits to slow down the output signal enough so you can actually see them toggling on the LED(s). ;)
(this may not be 100% correct, but this is to the best of my knowledge)...
In the always block, the statements below it will be evaluated every time the terms in the so-called "sensitivity list" are true.
The only thing in the sensitivity list in this example is the @(posedge clk).
This means that the count = count + 1 part will happen every time we see a rising edge of the clk input.
If you have only one statement after the always block, you don't need the "begin" and "end" words.
But, if you have more than one thing to evaluate on every rising edge of the clk, you could do this...
always @(posedge clk) begin
count = count + 1;
state = state + 1;
end
(we don't actually have a "state" register yet, but you get the idea). :)
Marcin Jurczuk btw, from the sort of videos you've watched, and your subs, I'm guessing your question was rhetorical, but thought I'd post some of my ramblings anyway in case somebody else wanted to know. lol
Thank you
Could you use a CPLD or FPGA and that universal active filter to emulate a SID chip?
yes, as long as it fits into the C64, and you have an adapter that has the right pins. You'd propably have to use a logic converter, as most modern FPGAs / CPLDs use 3.3v logic, but most older systems (6502, Z80, 8086 etc) used 5v
Anyone can share how to program an ALTER MAX2 EPM1270F256C5N?
"I type much slower since I lost my finger." - I'm sorry, what?
He fell off a ladder, hooked his wedding ring on a nail, and tore the flesh from his ring finger.
@@TheRealMentat001 That's yet one other reason not to get married...
@@TheRealMentat001 is he OK now?
Thanks for the video, but why in the world do you think we need to see your face all the time covering up the video?
Why so serious? Lets put a smile on that face!!
Keep hacking!
This guy gives me the impression he is talking to someone or something other than the youtube audience. Weird.