In this tutorial I will show how to program VGA interface in VHDL, suing DE1 Altera board. Eventually we will program a simple game ---------------------------------------------------- Source Code: github.com/Ant...
Excellent tutorial and very clear, especially the parts where you explain the different offsets to take into consideration, which others often forget to mention, thanks a lot ! :)
Thank you very much, Toni T800. Thanks to your video, we, students of Saint Petersburg State Polytechnic University, were able to do our course work. On the basis of your material we wrote the game Arkanoid. Thank you. Your video inspire us!
Anton,I truly appreciate the work you have put into these videos. This latest one, was just right. Please don't change the format from that. I would love to see more tutorials (at least yours are not demos) as I am absorbing a lot of info from these. Pity you left EEV Blog, you are a good resource and people can be just childish, very few critics put in the effort to produce an effort as good as this, if they post at all. I would love to see you expand these videos. Keep up the great work.
NIce videos bro, but you know it's difficult for beginners to follow you because you go straight to the VHDL code. It will be nice if make some high level block diagram showing the entities the signals and explain how you will proceed. and thank you
I followed your code on an Altera's DE10-Lite board and everything went fine *except* that I had to debounce the buttons, otherwise the squares would move erratically on the screen. I wonder why this wasn't necessary on your board? Anyway 2 thumbs up, great tutorials which helped me to get started with fpgas. Please do more of these!
Congratulation Toni!! firstly, thank you for these tutorials. you are so good,you help all the users of FPGA, hdl For me I have to load an image on a card DE1-SOC can you help me please to start my project . thank you very match
Best of luck with your thesis writing! Your FPGA videos and explanation are really amazing btw. Thank you for sharing your knowledge. I hope you get a chance to make some more videos.
Hi, thanks for the tutorials!!! question: how did you get the pixels for FP, BP, and SP? why there are differences between horizontal and verical FP, BP, and SP?
Hi After completing the Programmer for the code in the board that I am using, how can I display the content of the code on an external screen? I used a vga cable between the port and a side screen? Are there other things I should do..... I programmed the tic tac toi game and I programmed its code on the board (DE10-LITE) after that I used a vga cable to connect the screen to the board in order to display the game on the screen, but This did not happen. What is the problem and how can I display the game on the screen? Is there a specific step or thing that I must do... ***I am using quartus software from intel
Thank you for the tutorial, how about if I wanted to print out a big word in the middle of screen. is there a way to generated the pixel location corresponding to each letter?
Great tutorial brother . . . i have a question . . . i have a project to do . . i have got the top level module DE2_115_TOP.v, and several reusable cores developed by Altera: a VGA controller core Ctrl.v for synchronization signals. a reset module for resetting the PLL, and an Altera Megawizard components VGA_Audio_PLL.v. and i need to 2.Modify file DE2-115-TOP.v so that it controls the VGA to display colours according to the settings of the iSWs, especially: Red colour signal is controlled by the [17:12] bits of the switch; Green colour signal is controlled by [11:6] bits of the switch; Blue colour signal is controlled by [5:0] bits of the switch. Thank you
Hi Anton, thank you for your tutorials! They're really useful for a vhdl beginner! Can you provide also the code for this excercise? I will appreciate a lot. Thank you, Mattia
+Javier Núñez Keep in mind that you will have to display the total quantity of pixels (1688x1066) x 60 times per second which gives 107,96 MHz. Thats why you need 108MHz to display that resolution. DE1 has 3 internal clock sources, 24MHz, 27MHz and 50MHz, so you need to use a PLL to achieve 108MHz.
Hi Toni, i follow all the steps mentioned in the video, and on PLL, i just have one module name : altpll_0 =>pll_slave so i can't extract the signals CLKIN, CLKOUT, RESET. If you can help me to find out the problem i'll be grateful.
Dear Anton, i copy your source code but i can't compile the project because there is an error on PLL, i use the version of quartus 9.1 sp2 that don't have QSYS but only SOBC and when i try to set clock there are not all option that QSYS have, can you help me? consider that i must use 9.1 sp2 and i can't download the last version of Quartus
Awesome, Thank you, I have a problem with the code, my screen says me "Input signal out of range, change setting to 1920*1080 - 60 Hz", and then pass into sleep mode... I don't understand why that thing happen. Could you help me ? Thx
hi toni i've tried your tutorial but i have some error's in VHDL type. it says mismatch and std_logic doesn't match integer lateral. what that means ? help me please :)
I am really grateful for coming across your tutorial... :D but I am using the DE1 SoC and I have problem with the chip ADV7123, I watch a black screen, when I implement the vhdl code :/
Wow , thank you!!! I got the game working on my DE1 board, but I can't get the first project which display two white line crossing each other working? the display is always black no matter how I change the value of R,G,B.
i wanna thanks so much to explain very well i used DE1-SoC i change pin assignment according manual broad after run on screen no single so what is problem?
Just one question. How you know HSYNC is active low pulse for your monitor. As per VESA VGA STANDARD specs, it says HSYNC and VSYNC are active high pulses for 1280x1024 @60 Hz
MITU RAJ Most modern monitors aren't too fussy about the sync polarity for many common modes, at least via a VGA input. The sync is usually edge-triggered, so usually works OK, but what might happen is that the image gets shifted slightly, and that may or may not be possible to correct via the on-screen menu. The horizontal pulse are usually very short though, so the monitor triggering on either edge of the Hsync shouldn't be noticeable. The sync polarity is more of a historical thing, which helped older CRT monitors to detect the correct resolution (for safety blanking, and sync frequency limits etc.) But yep, it's probably worth sticking to the VESA standard modes if you want it to work on the majority of monitors (both old and new).
If anyone wants to see these exact tutorials, but done in Verilog I have completed them and posted them here: christopherhays.wordpress.com/ The code is also available here: github.com/christopherhays/my-modules Try it out and let me know if it works for you, I just prefer Verilog and maybe other people do as well.
Toni T800 Hi, I am try to run the basic code of VGA more or less that you explain to create the first image, but I have a DE2 -115 board, the assigments pin's and hardware is different(VGA ADC ADV7123) , then create the PLL with a clock of 50Mhz and additional PLL for VGA_CLOCK of VGA DAC , but didn't work . . any suggestion?
***** Hi. ADV7123 works a bit different. Check out this tutorial:th-cam.com/video/euw0ILLTEhM/w-d-xo.html I use DE1-SoC board there, it has the same ADV7123 chip as DE2-115. You can see how you should connect it to your entity in my sourcecode
If someone is using ADV7123, just make sure to tie BLANK and SYNC to Vcc, in order to be able to display what you are sending to R, G and B. Toni has 4 bits for each color because DE1 has a 4-bit DAC. Since ADV7123 is a 10-bit DAC, its equivalent... we just will have more color options in the end of the day. E.g. 4'b1111 in this video is equivalent to 10'b1111111111 in ADV...
Hey that's great! I'm new to this and I have no idea which pins I should assign to VGA_R, VGA_B and VGA_G. You use a 4 bit vector but the pins in the chip is size 10. Any help? Thanks!
hey anton plz i tried to achive 640x480 resolution by using the timing of it and using the same code of u but without pll and adding a code to achieve 25 clock of 50 clock coz my fpga is DE0 and nothing appear on the screen plz help me :(
sorry, I followed the tutorial but I can not show anything on the VGA monitor. could you explain how to assign PIN on the DE0 board...?? please.. I do not understand
Because any assignment will only become valid once the process has completed. e.g. The following if statement is satisfied after 1 clock cycle. PROCESS (CLK) BEGIN a 0) THEN ...do stuff END IF; END PROCESS; Processes are not executed sequentially. The same applies to HSYNC.
Hello Antoni. Congratullations for yor tutorial. Please, i have a DE2-115 board, and your solution dont work. Do you know what I need change to work? Thanks...
Thank you for the tutorial and great way of presenting, Toni I am trying with 1440* 900 and I got the FP and BP of it, however the screen still black after auto adjusting. am using DE2 Cyclone.
+Toni T800 you mean in PLL? I did, for my screen(1440*900) the out frequency about 106 Mhz. i made it 108 , or 104 these values are possible from my device frequency (27 MHz)
+Toni T800 I've tried to see the RGB values in simulation, they didn't appear error of ( Failed to open design unit file "VGA_01.vo" in read mode). is that related? I didn't figure out what it mean either, however synthesizing was successful.
+Ph.D Student Perhaps it is because the freq should be 106.47Mhz and your freq is way too off. Maybe. If you can, try other resolutions where you can achieve clock freq. much closer. BTW, your board has also 50 Mhz clock source, see if you can generate better signal with it. PS Also make sure the BP and FP are right. I always take right data from this site: tinyvga.com/vga-timing
+Toni T800 Thank you Toni. I used only one clock bit, how can I assign two clk bits to one clock pin?. However, I am using this web to get the info, you know , when the frequency far away the screen shows " Change the resolution to 1440*900" and screen going to sleep , but when I tried the 1.4 the screen just go black and still operating. Seems the R,G,B NOT shown.
Hi Anton, I just want to explain the problem, you didn't mention about blank signal , and also the VGA clk to be output taking its value from the FPGA clk, these are some resons why it didn't work with me... regards.
+Ph.D Student Hello, you managed to make the project work in DE2-115? I'm trying on DE2, the same video resolution, but do not get hit. I am using 27MHz clock the FPGA, but it does not have two outs, how you resolved this issue?
+João Paulo Fernandes de Cerqueira César No matter the resolution, most LCD monitors nowadays are self adjusted, however I worked with 800*600. you only need to drive the VGA clk which which is a pin in DE2 , you may use the PPL as Toni did. Be sure to utilize all the VGA pins ( Assign Values to them) .
+João Paulo Fernandes de Cerqueira César Blank = (videoh and videov) , videoh =1 when you are in horizantal visible pixels range ( I mean in places other than synchronization ones) same for videoh.
Thank you for your video, I have a problem i try to make it with cyclone V DE1-soc and this model don´t have Avalon PLL I try used Altera PLL clock input 50 Mhz and output 108Mhz but nothing T-T, please help me with this problem
Angel Gabriel Valencia Huaman hi. De1 and DE1SoC are a bit different. Take a look at this tutorial: th-cam.com/video/euw0ILLTEhM/w-d-xo.html I use DE1-SoC there, and have an example on how to use VGA output on this board.
Hey Toni, How did you know the display mode. I wanted to do 640x480 and am not sure what I should be looking up to figure mine out. Also, I am trying to do this on a DE2-115, so what areas would you say I should pay particular attention to change details on my board.
Thanks, by the way, if I'm using a 50 MHz clock for the rest of my project is there a reason to use the 24MHz clock used here or can I switch easily to that (for 640 x 480 with the pixel padding it has 800 x 525 x 60 = 25.2 MHz so I switch to that as well right instead of 108 MHz).
The 24 MHz clock is defined as vector in the pin assignment file. CLOCK_24(0) is 180° shifted relativ to CLOCK_24(1), so when one has a rising edge, the other has a falling edge.
Thanks Toni. Also, for your VSYNC you are using from 0 to 4 even though you said that between front porch and back porch you should force low, Does that mean if I'm using 640x480 where Front porch 10 Sync pulse 2 I should be doing IF(VPOS>9 AND VPOS10 AND VPOS9 AND VPOS
Excellent tutorial and very clear, especially the parts where you explain the different offsets to take into consideration, which others often forget to mention, thanks a lot ! :)
Thank you very much, Toni T800. Thanks to your video, we, students of Saint Petersburg State Polytechnic University, were able to do our course work. On the basis of your material we wrote the game Arkanoid. Thank you. Your video inspire us!
+Василий Васильев Всегда пожалуйста ;)
Thank you for the great video, the subtitles were a huge help with tracking the numbers.
Hello, you can find the link to the source code below in the video description.
Anton,I truly appreciate the work you have put into these videos. This latest one, was just right. Please don't change the format from that.
I would love to see more tutorials (at least yours are not demos) as I am absorbing a lot of info from these.
Pity you left EEV Blog, you are a good resource and people can be just childish, very few critics put in the effort to produce an effort as good as this, if they post at all.
I would love to see you expand these videos. Keep up the great work.
Incredible simple tutorial for something not so trivial. I learned a lot. tahnk you very much
NIce videos bro, but you know it's difficult for beginners to follow you because you go straight to the VHDL code. It will be nice if make some high level block diagram showing the entities the signals and explain how you will proceed. and thank you
Thank you so much man, you have made my work so much more easy, I am really grateful for coming across your tutorial . YOu are the best :) !
awesome tutorial!
worked on a NEXSYS 4 DDR Artix-7 board.
and of course thank you so much for publishing this video... It has helped me understand vga output a lot more quickly than I would have otherwise
Thank you for the tutorial, keep doing videos. greetings from Colombia
I followed your code on an Altera's DE10-Lite board and everything went fine *except* that I had to debounce the buttons, otherwise the squares would move erratically on the screen. I wonder why this wasn't necessary on your board? Anyway 2 thumbs up, great tutorials which helped me to get started with fpgas. Please do more of these!
Congratulation Toni!!
firstly, thank you for these tutorials. you are so good,you help all the users of FPGA, hdl
For me I have to load an image on a card DE1-SOC
can you help me please to start my project .
thank you very match
Excellent work
Thanks alot... u are a savior :) ... great work!!!!
Антуан, ю ар зэ бэст!
why have you stopped making vhdl videos, they are great! make more.
Hi. Thanks for nice words! I will do more video in future. Right now I am writing my Master Thesis, so no time/energy for FPGA magic:)
Best of luck with your thesis writing! Your FPGA videos and explanation are really amazing btw. Thank you for sharing your knowledge. I hope you get a chance to make some more videos.
What is your Masters Thesis about?
Thanks a lot :) because of you we could make some progress :)
Hi,
thanks for the tutorials!!!
question: how did you get the pixels for FP, BP, and SP? why there are differences between horizontal and verical FP, BP, and SP?
great tutorial
Never mind. I got it. I copy the code incorrectly. Again, thank you for uploading this!!
Thank you for the tutorial but when i try to use the code for 1280*1024 i got in the monitor "auto adjusting". what that means ?
Please do you link just the cable vga with FPGA and any screen?
Hi
After completing the Programmer for the code in the board that I am using, how can I display the content of the code on an external screen? I used a vga cable between the port and a side screen? Are there other things I should do..... I programmed the tic tac toi game and I programmed its code on the board (DE10-LITE) after that I used a vga cable to connect the screen to the board in order to display the game on the screen, but This did not happen. What is the problem and how can I display the game on the screen? Is there a specific step or thing that I must do...
***I am using quartus software from intel
Thank you for the tutorial, how about if I wanted to print out a big word in the middle of screen. is there a way to generated the pixel location corresponding to each letter?
Amazing! Tks bro!
Great tutorial brother . . . i have a question . . . i have a project to do . . i have got the top level module DE2_115_TOP.v, and several reusable cores developed by Altera: a VGA controller core Ctrl.v for synchronization signals. a reset module for resetting the PLL, and an Altera Megawizard components VGA_Audio_PLL.v.
and i need to 2.Modify file DE2-115-TOP.v so that it controls the VGA to display colours according to the settings of the iSWs, especially: Red colour signal is controlled by the [17:12] bits of the switch; Green colour signal is controlled by [11:6] bits of the switch; Blue colour signal is controlled by [5:0] bits of the switch.
Thank you
great tutorials man! what vhdl program is that you use? i use xilinx but this one seems more friendly, i´m kind of new in vhdl
+Luis Zurita This is Quartus, official free Altera Software
Hi Anton,
thank you for your tutorials! They're really useful for a vhdl beginner!
Can you provide also the code for this excercise? I will appreciate a lot.
Thank you, Mattia
Does the cyclone v board work in the same way?
Awesome...
But I do not understand why do you need a 24 MHz clock to create an 108MHz clock ?
Thanks
The demo board probably has a 24Mhz oscillator and his program needs to run at 108Mhz
+Javier Núñez
Keep in mind that you will have to display the total quantity of pixels (1688x1066) x 60 times per second which gives 107,96 MHz. Thats why you need 108MHz to display that resolution.
DE1 has 3 internal clock sources, 24MHz, 27MHz and 50MHz, so you need to use a PLL to achieve 108MHz.
@@Baqueirooo thanks for this useful informations
Thank you for your excellent videos. I have a question; How can we display any TEXT on vga display? May you help me.
Thanks a lot for the help but can u give any tips how to connect this vga to make an audio equalizer?
Congratulations.
Hi, I cannot move one of the squares, I don't understand why. Please help me!
Epic ! Tony rules !
Hi Toni, i follow all the steps mentioned in the video, and on PLL, i just have one module name : altpll_0 =>pll_slave so i can't extract the signals CLKIN, CLKOUT, RESET. If you can help me to find out the problem i'll be grateful.
The same probleme .I am using quartus 8
I am making an architecture of computer class on youtube, and i will use your code but i will give the reconize to your work
Regards
Dear Anton, i copy your source code but i can't compile the project because there is an error on PLL, i use the version of quartus 9.1 sp2 that don't have QSYS but only SOBC and when i try to set clock there are not all option that QSYS have, can you help me? consider that i must use 9.1 sp2 and i can't download the last version of Quartus
Awesome, Thank you,
I have a problem with the code, my screen says me "Input signal out of range, change setting to 1920*1080 - 60 Hz", and then pass into sleep mode... I don't understand why that thing happen. Could you help me ? Thx
that is just mean you are driving your vga display at wrong resolution/timing
hi , i have question , can you help me ?
how i can add a Moving Target to display for a game ?
hi toni
i've tried your tutorial but i have some error's in VHDL type. it says mismatch and std_logic doesn't match integer lateral. what that means ? help me please :)
I am really grateful for coming across your tutorial... :D but I am using the DE1 SoC and I have problem with the chip ADV7123, I watch a black screen, when I implement the vhdl code :/
Wow , thank you!!! I got the game working on my DE1 board, but I can't get the first project which display two white line crossing each other working? the display is always black no matter how I change the value of R,G,B.
i wanna thanks so much to explain very well i used DE1-SoC i change pin assignment according manual broad after run on screen no single so what is problem?
Hello, do you have any Altera DE 1 Cyclone ii serial communication tutorial? Like DE1 board send serial data with bluetooth module?
you are awesome , thanks a lot,
a have a question , whats the difference between process and procedure?
How could you make this square into a circle?
AMAZING
thanks toni! your quartus complier run very fast. do you have license crack altera quartus 14.1? how do you send to me?
Excellents videos! Excuse me, What program do you use for making your videos? I´m interested in the part of the subtitles.
Hi. I am using CorelVideo Studio
Thank you!
Just one question. How you know HSYNC is active low pulse for your monitor. As per VESA VGA STANDARD specs, it says HSYNC and VSYNC are active high pulses for 1280x1024 @60 Hz
MITU RAJ
Most modern monitors aren't too fussy about the sync polarity for many common modes, at least via a VGA input.
The sync is usually edge-triggered, so usually works OK, but what might happen is that the image gets shifted slightly, and that may or may not be possible to correct via the on-screen menu.
The horizontal pulse are usually very short though, so the monitor triggering on either edge of the Hsync shouldn't be noticeable.
The sync polarity is more of a historical thing, which helped older CRT monitors to detect the correct resolution (for safety blanking, and sync frequency limits etc.)
But yep, it's probably worth sticking to the VESA standard modes if you want it to work on the majority of monitors (both old and new).
Thanks bro ..
thanks for that, but i need an example for the HDMI please
Why u've taken 2 bit vector for clk in main program
If anyone wants to see these exact tutorials, but done in Verilog I have completed them and posted them here: christopherhays.wordpress.com/
The code is also available here: github.com/christopherhays/my-modules
Try it out and let me know if it works for you, I just prefer Verilog and maybe other people do as well.
@Toni T800
I have an altera de2i-150 fgpa board will it work on there too? Or do I have to change something on the code to make it work?
Did you figured out what to do on the DE2-115 to make this work?
Please if someone can tell why we have just one RGB in the procedure and not R and G anb B ? how do the procedure use RGB ?
Thank you for the video, I have a question, how do you know or how did you find your pixelclock?
***** just google the VGA interface, You will find a list of pixelclock frequenzy for each resolution
Toni T800 Hi, I am try to run the basic code of VGA more or less that you explain to create the first image, but I have a DE2 -115 board, the assigments pin's and hardware is different(VGA ADC ADV7123) , then create the PLL with a clock of 50Mhz and additional PLL for VGA_CLOCK of VGA DAC , but didn't work . . any suggestion?
***** Hi. ADV7123 works a bit different. Check out this tutorial:th-cam.com/video/euw0ILLTEhM/w-d-xo.html
I use DE1-SoC board there, it has the same ADV7123 chip as DE2-115. You can see how you should connect it to your entity in my sourcecode
thanks!!
If someone is using ADV7123, just make sure to tie BLANK and SYNC to Vcc, in order to be able to display what you are sending to R, G and B. Toni has 4 bits for each color because DE1 has a 4-bit DAC. Since ADV7123 is a 10-bit DAC, its equivalent... we just will have more color options in the end of the day. E.g. 4'b1111 in this video is equivalent to 10'b1111111111 in ADV...
Hey that's great! I'm new to this and I have no idea which pins I should assign to VGA_R, VGA_B and VGA_G. You use a 4 bit vector but the pins in the chip is size 10. Any help? Thanks!
hey anton
plz i tried to achive 640x480 resolution by using the timing of it
and using the same code of u but without pll and adding a code to achieve 25 clock of 50 clock coz my fpga is DE0
and nothing appear on the screen plz help me :(
sorry, I followed the tutorial but I can not show anything on the VGA monitor. could you explain how to assign PIN on the DE0 board...?? please.. I do not understand
Watch my first tutorial (Blinking LED), I show how to assign pins at the beginning.
Hey quick question:
So I understand why hsynch is low between fp and bp, but why is vsynch thrown low between 0 and 4 instead of 1 and 4?
Because any assignment will only become valid once the process has completed. e.g. The following if statement is satisfied after 1 clock cycle.
PROCESS (CLK)
BEGIN
a 0) THEN
...do stuff
END IF;
END PROCESS;
Processes are not executed sequentially. The same applies to HSYNC.
plz some help, how to bring the window at 10:58 (to attach the generated file to our project), im gonna thankful to have some answer ^^ .
Why have you used 12 bits instead of 8?
can you also post the first version SYNC, because I can't get the first time working.
how to map the sine wave? could you tell me?
nice!
Hi Anton, how are you?.
Please, could you do a tutorial about using SDRAM?.
I will thank you a lot.
Hug!
Hello Antoni. Congratullations for yor tutorial.
Please, i have a DE2-115 board, and your solution dont work. Do you know what I need change to work? Thanks...
Did you figured out what to do on the DE2-115 to make this work?
Hello..
that use a 2-bit signal at input CLOCK_24 signal instead of a 1-bit?
hi.
CLOCK_24 on DE board is double 24 MHZ clock output. One is just inverted.So while Clock_24(0) is LOW, the Clock(1) is HIGH.
thaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaank you very much
Your bottom subtitles are obnoxious, Anton. Those who do need subtitles can get them with youtube itself (it does a good job doing that).
Thank you for the tutorial and great way of presenting, Toni I am trying with 1440* 900 and I got the FP and BP of it, however the screen still black after auto adjusting. am using DE2 Cyclone.
+Ph.D Student Did you also changed the VGA frequency?
+Toni T800 you mean in PLL? I did, for my screen(1440*900) the out frequency about 106 Mhz. i made it 108 , or 104 these values are possible from my device frequency (27 MHz)
+Toni T800 I've tried to see the RGB values in simulation, they didn't appear error of ( Failed to open design unit file "VGA_01.vo" in read mode). is that related? I didn't figure out what it mean either, however synthesizing was successful.
+Ph.D Student Perhaps it is because the freq should be 106.47Mhz and your freq is way too off. Maybe.
If you can, try other resolutions where you can achieve clock freq. much closer.
BTW, your board has also 50 Mhz clock source, see if you can generate better signal with it.
PS
Also make sure the BP and FP are right. I always take right data from this site:
tinyvga.com/vga-timing
+Toni T800 Thank you Toni. I used only one clock bit, how can I assign two clk bits to one clock pin?.
However, I am using this web to get the info, you know , when the frequency far away the screen shows " Change the resolution to 1440*900" and screen going to sleep , but when I tried the 1.4 the screen just go black and still operating. Seems the R,G,B NOT shown.
hello Anton ,thanks a lot for the tutoiral
Can u please provide the source code in verilog for the same?
what is the purpose of the libraries?
Hi Anton, I just want to explain the problem, you didn't mention about blank signal , and also the VGA clk to be output taking its value from the FPGA clk, these are some resons why it didn't work with me... regards.
+Ph.D Student Hello, you managed to make the project work in DE2-115? I'm trying on DE2, the same video resolution, but do not get hit. I am using 27MHz clock the FPGA, but it does not have two outs, how you resolved this issue?
+João Paulo Fernandes de Cerqueira César No matter the resolution, most LCD monitors nowadays are self adjusted, however I worked with 800*600. you only need to drive the VGA clk which which is a pin in DE2 , you may use the PPL as Toni did. Be sure to utilize all the VGA pins ( Assign Values to them) .
+Ph.D Student Thanks! How you assign the VGA_BLANK signal?
+João Paulo Fernandes de Cerqueira César What value I need to put into this signal?
+João Paulo Fernandes de Cerqueira César Blank = (videoh and videov) , videoh =1 when you are in horizantal visible pixels range ( I mean in places other than synchronization ones) same for videoh.
Thank you Shia LaBeouf!
Hello, can you make a tutorial in making a sudoku game in fpga? thank you it will be a great help. Thank you very much!
Hello Veronica. I am sorry, but i only have experience with Altera IDE, so i can't help you with Xilinx.
can help me with the PIN assignment..
Hello Anton, thank you for your help... I need pll.vhd to xilinx. Can you help me? thanks!
Hi, i am not able to get this code from the given site. Can you show me another way to get this? thanks
Salman Farsi Hi, check the new link in the video description.
Toni T800 thanks man...
Helo, the number of FP,BP and SP pixels depends on resolution etc.
Here is more information
tinyvga. com/vga-timing
Thank you for your video,
I have a problem i try to make it with cyclone V DE1-soc and this model don´t have Avalon PLL I try used Altera PLL clock input 50 Mhz and output 108Mhz but nothing T-T, please help me with this problem
Angel Gabriel Valencia Huaman
hi.
De1 and DE1SoC are a bit different.
Take a look at this tutorial: th-cam.com/video/euw0ILLTEhM/w-d-xo.html
I use DE1-SoC there, and have an example on how to use VGA output on this board.
Toni T800 , thank you!
you are de best :) I will try to do it right now...thank you very much! really
Angel Gabriel Valencia Huaman I do this right now and had same problem. SO if it works for you, I'll be thankful for informations
Hello
I also work with a De1-SOC card.
could you help me please.
Thank you very much
i love you
may i have this is verilog
Hey Toni,
How did you know the display mode.
I wanted to do 640x480 and am not sure what I should be looking up to figure mine out.
Also, I am trying to do this on a DE2-115, so what areas would you say I should pay particular attention to change details on my board.
Hello. Here is the specific timing for different resolution/formats:
tinyvga.com/vga-timing
Thanks, by the way, if I'm using a 50 MHz clock for the rest of my project is there a reason to use the 24MHz clock used here or can I switch easily to that (for 640 x 480 with the pixel padding it has 800 x 525 x 60 = 25.2 MHz so I switch to that as well right instead of 108 MHz).
Something else that's really been throwing me off is why do you have a CLOCK_24 vector? Wouldnt STD_LOGIC suffice?
The 24 MHz clock is defined as vector in the pin assignment file. CLOCK_24(0) is 180° shifted relativ to CLOCK_24(1), so when one has a rising edge, the other has a falling edge.
Thanks Toni. Also, for your VSYNC you are using from 0 to 4 even though you said that between front porch and back porch you should force low, Does that mean if I'm using 640x480 where
Front porch 10
Sync pulse 2
I should be doing
IF(VPOS>9 AND VPOS10 AND VPOS9 AND VPOS
็How assignment editor of KEYS and SW at Qsys please !!!!!!!!!!
พงศ์พิณิช ทรงปั่น Use PIO component in Qsys!!!!!!!!!!!!!!!111
de2 plz
Hi, I think that the link are dead :/
Thank you a lot for this tutorial anyway :)
***** Hi, i finally found this project and uploaded it to github.Check the link in the description:)
Toni T800 So nice! Many thanks ^^
No, sry. I only code in VHDL.
Антон привет мне нужна помощь отзовись
WTF is with everyone and VHDL? This thic boi needs verilog yo.