This is reavealing why RISC-V is such a good instruction set. Fixed rotates, simple non moving bits.. you can almost negate any real microcode, just straight up combinational logic on a few bits. Give a few fixed shift offset wires, wire up register select to the instruction.. it's genius. Even a 5602 is complicated compared to the decoding of these in silicon.
Yeah, They did a pretty good job with RISC-V! I hope to do more with it at some point. The base ISA is simple enough to try a stab at some FPGA implementations.
This is one of the best guides I've ever seen, thank you so much! I don't know if I would've been able to figure out how to do branch statements without your diagram.
You and me both! It wasn't until I found myself sketching them out by hand that I realized a) how they work and b) that I am likely not alone and that releasing even a 1/2 finished document with them in it would be a good thing. Thank you for your such kind words!
It's amazing how well you describe all of the technical details and still keep my attention. Great video! I had an idea to try to write an RV32I emulator in CPP and compile it to run on itself. Seems practical after watching this video!
Thanks! If you are looking for ideas, here is a 3-part assignment I gave my students a while back on writing their own: github.com/Architecture-And-Organization/Memory-Simulator/releases/download/2022-fall/handout.pdf github.com/Architecture-And-Organization/RV32I-Disassembler/releases/download/2022-fall/handout.pdf github.com/Architecture-And-Organization/RV32I-Simulator/releases/download/2022-fall/handout.pdf There are also some videos in the course lectures where I show them how to add a thin layer to this design so that it can run multiple cores (See the course web site in the video description.)
Thanks! It turns out that understanding the rationale for the format of the immediate operands is what drove me to consolidate and post my notes on related assembly language topics and draw the 'ribbon' pictures that illustrate the untangling of the immediate bits.
@@JohnsBasement Really enjoying your RISC-V series. I wish my professors in college were as clear as you. Thanks for making your videos public. Surprised your channel hasn’t gotten more traction by now!
It took me time to understand that I do not need to calculate the offset relative to the address myself(for B-type instructions). The compiler will do it for me. Maybe I didn't listen carefully :( Thank you very much for this playlist!
When extracting the function/data from the instructions (for the disassembler ~14:00), i would shift first and then AND. f3 = (I & 0x00007000) >> 7; vs f3 = (I >> 7) & 0x7;
It probably doesn't really matter but it seems like the minor opcodes are chosen kind of randomly. Why is the funct3 for a left shift given a 1 and a right shift a 5?
This is a good question. I haven't researched this one yet. It might have to do with an ALU design that can be optimized for reuse in the conditional branch instructions.
Try now. I removed the year & semester from the link. BUT now it is for the spring and the RV32I stuff is not yet posted. [I suppose this is one of the downsides of leaving copies of my university lectures on TH-cam.] Anything in particular that you are looking for?
hello, in my final exam lecturer asked me that from lw x1 1(x2) where x=1 x=2, what is value of a3 and wd3 also srca and srcb. there was no additional info and i think its impossible to find them without it. and he said you should write but how?
@@lamiiia3037 Well, it would depend on the implementation of the CPU. If it does not allow unaligned loads then the instruction would be illegal because it would be reading from x2+1 which would be 3 (not a multiple of 4). If the CPU *does* allow unaligned loads then it would put the 4-byte value read from address 3 into x1. To know the values you'd need to know what is in memory. See also: stackoverflow.com/questions/68245606/risc-v-ram-address-alignment-for-sw-sh-sb
![[#2024MAMA] BIGBANG (빅뱅) - 뱅뱅뱅 (BANG BANG BANG) + FANTASTIC BABY | Mnet 241123 방송](http://i.ytimg.com/vi/EQsYfiPR9uM/mqdefault.jpg)
This is reavealing why RISC-V is such a good instruction set. Fixed rotates, simple non moving bits.. you can almost negate any real microcode, just straight up combinational logic on a few bits. Give a few fixed shift offset wires, wire up register select to the instruction.. it's genius. Even a 5602 is complicated compared to the decoding of these in silicon.
Yeah, They did a pretty good job with RISC-V! I hope to do more with it at some point. The base ISA is simple enough to try a stab at some FPGA implementations.
This is one of the best guides I've ever seen, thank you so much! I don't know if I would've been able to figure out how to do branch statements without your diagram.
You and me both! It wasn't until I found myself sketching them out by hand that I realized a) how they work and b) that I am likely not alone and that releasing even a 1/2 finished document with them in it would be a good thing.
Thank you for your such kind words!
This is the best RISC-V video that I have seen. I reproduced your table in a ϕText document.
Thank you. Glad you liked it!
It's amazing how well you describe all of the technical details and still keep my attention. Great video! I had an idea to try to write an RV32I emulator in CPP and compile it to run on itself. Seems practical after watching this video!
Thanks!
If you are looking for ideas, here is a 3-part assignment I gave my students a while back on writing their own:
github.com/Architecture-And-Organization/Memory-Simulator/releases/download/2022-fall/handout.pdf
github.com/Architecture-And-Organization/RV32I-Disassembler/releases/download/2022-fall/handout.pdf
github.com/Architecture-And-Organization/RV32I-Simulator/releases/download/2022-fall/handout.pdf
There are also some videos in the course lectures where I show them how to add a thin layer to this design so that it can run multiple cores (See the course web site in the video description.)
@@JohnsBasement Wow thanks! I will definitely take a look at that
Great lecture! You're so good at simplifying and clarifying concepts, John! In addition, John Lithgow-like voice sounds so clear.
Thanks!
Thank you for the video sir, this has been incredibly helpful in making my own riscv processor. Also the instruction set made coding it much easier.
Glad to know it helped!
Great video! Helped me understand the funky immediate business going on with B and J type instructions
Thanks! It turns out that understanding the rationale for the format of the immediate operands is what drove me to consolidate and post my notes on related assembly language topics and draw the 'ribbon' pictures that illustrate the untangling of the immediate bits.
@@JohnsBasement Really enjoying your RISC-V series. I wish my professors in college were as clear as you. Thanks for making your videos public. Surprised your channel hasn’t gotten more traction by now!
Beautifully explained.
Thank you for such kind words!
Thanks for the very well explained pdf and video
It took me time to understand that I do not need to calculate the offset relative to the address myself(for B-type instructions). The compiler will do it for me. Maybe I didn't listen carefully :(
Thank you very much for this playlist!
Sorry 'bout that. 😕. This lecture assumes a familiarity with assemblers, labels and so on.
When extracting the function/data from the instructions (for the disassembler ~14:00), i would shift first and then AND.
f3 = (I & 0x00007000) >> 7; vs f3 = (I >> 7) & 0x7;
Any particular reason?
Thank you very much. Well explained. I understand the subject way better now.
Glad to hear that!
Thanks a lot.
Amazing video!
Thanks!
ths is thoe one of the bet guidance . sir I am requesting you to send me the pdf of this book sir please
See the link to it in the video description. There are PDF under a tab called Releases.
thank you.
You are welcome.
well informative
Thanks!
It probably doesn't really matter but it seems like the minor opcodes are chosen kind of randomly. Why is the funct3 for a left shift given a 1 and a right shift a 5?
This is a good question. I haven't researched this one yet.
It might have to do with an ALU design that can be optimized for reuse in the conditional branch instructions.
Only one bit differs. It’s actually quite wise
hi john, i'm unable to open the website mentioned in the description, it would be helpful if you look in to this issue.
Try now. I removed the year & semester from the link. BUT now it is for the spring and the RV32I stuff is not yet posted. [I suppose this is one of the downsides of leaving copies of my university lectures on TH-cam.] Anything in particular that you are looking for?
@@JohnsBasement thanks for the response, I just needed to look in to the website,to get more general information nothing specific
Hi, could you tell me where i can find your pdf book please?
Click the GitHub link in the video description.
is there a link to the pdf?
In the releases page for the github RVALP project.
39:39 I am only here for this. Without this diagram, it is impossible to understand this mess.
Grab a copy of the PDF! See the links in the description below the video.
@@JohnsBasement Thanks, I just did. I bough myself a Sipeed Nezha Risc-V SBC Linux and I am experiementing with assembly.
thank u sir.
can we please get the file u r using in the video!
RVALP? Look in the video description.
@@JohnsBasement
I got it thanks alot
That was a 🔐 unexceptional illustration. Just as any other day
Thanks!
hello, in my final exam lecturer asked me that from lw x1 1(x2) where x=1 x=2, what is value of a3 and wd3 also srca and srcb. there was no additional info and i think its impossible to find them without it. and he said you should write but how?
I don't understand the notation you are using in this question. x1 and x2 are register names. What does x=1 and x=2 mean? What are srca and srcb?
@@JohnsBasement x1 register contains 1 and x2 2. srcA comes from rd1 srcB comes extender. its risc-v single cycle processor
@@lamiiia3037 Well, it would depend on the implementation of the CPU. If it does not allow unaligned loads then the instruction would be illegal because it would be reading from x2+1 which would be 3 (not a multiple of 4). If the CPU *does* allow unaligned loads then it would put the 4-byte value read from address 3 into x1. To know the values you'd need to know what is in memory.
See also: stackoverflow.com/questions/68245606/risc-v-ram-address-alignment-for-sw-sh-sb