design verification flow of any industry standard project or protocol with UVM,UVM part1

[@sravani7567]

Master work like tb and slave work design what will happen??

[@mupparapukeerthichandh8145]

Do we need to use sanity testcases only when we deal with registers in our project

[@FreeVLSIDVtrainingbyDEVTALLURI]

except bridge protocols

[@LingaGaneshKumar]

Hi sir, how can i join your classes ??

[@FreeVLSIDVtrainingbyDEVTALLURI]

9182686908..text to this number