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Use logic data type in interface

Sir send the link to download or the link is paid..?

preamble....101010...

Can we get this PPT? Please

link sir

Well defined course sir, looking forward for the same

Payload data minium 46Bytes with included header data also or not..??

Master work like tb and slave work design what will happen??

Please wait

Please sir dpi, whenever u upload videos I come to see whether it is dpi or not

Sir can you please tell how if we want to add only certain signals to waveform how to write the code for that sir. Like if i have full adder with a,b,c inputs and s,c outputs i want to see only a,b,s then what to do sir

Sir why dont we use objections in run_phase tasks of monitor and driver , but in test class we use objections of its run_phase.

good for the start

Hi , Can you share the presentation ?

Clk,rst connect to slave or dut not to master.suppose if we use interconnect then to verify it, that will become dut.take i/o direction wrt to slave or dut here..

Around 1 hr...u can sample i/O's at same clk edge also, subject to spec

Plz any one reply me

Sir A expression a ##3 b Means excluding present clock edge or including present clock edge

Hello sir ,waiting for APB 3 with state diagram

Thanks

Never stop teaching us sir ✨🙏video is very effective,.I have seen other channel video but they won't clear particular topic but u if u take any topic u take so much time on that topic to make us clear ♥️ other channel just skip the topic they won't go depth

Sir your explanations are very good. It will be really helpful to us if you make videos on AHB protocol.

Thank you

Much awaited sir, thank you

Sir could u make a video on how can we weite different sequence class from 1 transaction(sequnce item) based on whay please make one video on this sir

Also thank you for continuously uploading uvm now ♥️✨

Sir please dpi ?!

in wrap lower boundary calculation 32'h0000_0010 = 16 (decimal) , so 16/24 = 0.666, so 16-16/24 cannot be equal to 8. can you please explain this. (at the time 56:00 of this video)

Hello sir, I have some questions related to writing the design code .Whether we have to write verilog design code for both master and slave ? or we have to write only for slave considering it as ram like memory and considering master as Testbench?

32'h102/2

remove the name intf on both boxes around 30

neglect lectrure from time 25 to 27

at time 24 ,out of 2 lines,one line is belongs to slave interface

Sir 1 doubt diff testcases nothing but different sequence class or diff sequence item class??

Eagerly waiting for your next video on Ethernet

Dev, you have given clear explanation for what you have explained. Thanks for posting, looking forward to listening more videos on Ethernet Topic. Thank you Dev

Hi sir when we can expect remain uvm classes

Thanks for explaining us the real time scenarios in very detailed manner sir .I got the answers for the doubts I raised in the previous video.Thank you so much for the response.I have few more doubts related to TLM Ports. Could you please explain the real time scenarios of when import and export should be used? And also I am assuming monitor to scoreboard communication can be considered as child to parent class communication.please correct me if I am wrong. In the similar way when should the parent to child class communication happens with respect to UVM Components?

Tq so much sir for uploading ethernet

Thanks for the clear explanation sir, the session was very informative.I have a doubt related to the response coming from driver to sequence item through sequencer. Could you please explain what the response actually contains? and what is the use of the response? How the response sending from dut to driver is different from the response sending to the monitor by DUT? My another doubt is Will the sequencer send the another transaction from Sequence item only when it get the response for the previous transaction from the DUT?

Thank you so much I was waiting for UVM♥️

Thank you sir, I was waiting for the lecture.

Eagerly waiting for next videos sir

Thank you for your efforts sir. I always wait for your lectures to get uploaded. I sleep after watching the lecture even it's midnight. Please upload the lectures on daily basis sir. If I do not see new lecture, my day feels incomplete. Your lectures are informative, interesting and priceless. No words for your efforts sir.

Hello sir where can i access uvm from the beginning sir? Recoding!?

Uvm please sir from factory

Your work is inspiring freshers like me. Your explanation is excellent and you delivered important and sufficient information to us. In some topics while we learning, we unable to think beyond the boundary but those doubts you only questioned yourself and posted those important topics like you explained last part of this video. Thank you very much keep posting videos. If possible do one video how can we think if we want to become best Design Verification Engineer and in order to crack interview what and all thing we need to focus more. Please do favour to us. Once again thank you sir.

If recoding season already there means tell us sir please will buy that(UVM)