What is x86-64-v3? Understanding the x86-64 microarchitecture levels
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- เผยแพร่เมื่อ 5 ก.พ. 2024
- Those who follow the Linux related news will have noticed the term x86-64-v3 being used recently. What is x86-64-v3? What is all the fuss? What is its relationship to Linux? Is it important? Let's find out!
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Two nits: i686 was introduced in the Pentium Pro; and, you do find a lot of Intel Atom processors in embedded products like NAS devices, network firewalls, control planes for switches. While some of those are moving to Xeon D or newer Atom processors with Gracemont or newer Atom cores, requiring v3 will be a tougher sell for those markets than for the consumer markets.
It is a chip architecture which is on its way out which is inefficient and Bloated with so many hidden spyware instructions from the likes of Intel and even AMD.
I think debbie-anne linux is a great idea to get more women into Linux😂
So basically, it's a marketing thing. That's why big companies designed they own computers and OSs.
I came about this a long while back when I was trying to download an update for mpv-player and there was an x86 64 V3 version, but there was a post explaining what it was so it was all good.
Might as well just make a replacement for x86 at this point, it's becoming a compatibility nightmare. Like a x86-64 without all the instructions that aren't really needed anymore, and just revise it every few years whilst keeping compatibility in mind.
Can't copywrite names. Pentium isnt Copywrite it is Trademarked :)
No, 32 bits was not given up ... every single intel CPU yet can run a 32 bit OS, the backward compatibility is still there, all the way to mov al,2 in 8 bit. That is the beauty and very often advantage of x86, it may change in a near future.
It's kind of uncommon & confusing in calling these microarchitectures, because in the recent processor architecture world the word microarchitecture specifically already means something different. Instead it's more appropriate & common to either call these architecture extensions or subarchitectures.
x86 as a CISC unit is kinda bloated too much already, with huge die area covered by almost never used instruction handlers. And now we get new ISA with even more bloat? Does it worth it? I wonder if extended instruction sets actually give any noticeable performance over old CISC or RISC architectures. Depends on application and compiler i guess, but as of now, LLVM Clang has very weak, almost negligible optimisation for latest x86 ISAs, same with gcc iirc. To me personally, it seems as just a pure marketing and potentional threat of hardware bitlocking, like it’s already happening with new TPM and Secure Boot modules, which obviously are created to try and let microsoft monopolize OS market and keep you from your right to own your devices(like it’s already happened with your phones).
There is another reaason v3 support as requirement will get harder: Most office Linux users won't actually performance wise require to update their CPUs beyond a pre v3 point, as the demand on the hardware hasn't increased much outside of gaming in recent years.
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If I remember correctly the 80386 used a memory controller that was located in the Northbridge, which at the time was a separate chip from the CPU. Today the Northbridge is part of the CPU, so we really don't mention it much anymore.
Thanks for this well done and informative video.
Intel really held back v3 adoption. Also if anyone is wondering about small cores and meeting v2 requirement, Silvermont and up on the Atom lineup and Jaguar and up on AMD’s cat core lineup meet v2 requirements.
Am I the only one who gets frustrated by the use of Intel CPU codenames? Everyone seems to do that when talking about instruction sets and such, and I always have to go look up to see which processor it actually is, to be able to have a point of comparison with CPUs I actually know and/or own.
AVX-5 1 12 never heard of that instruction set
"Intel does not officially support AVX-512 family of instructions on the Alder Lake microprocessors. Intel has disabled in silicon (fused off) AVX-512 on recent steppings of Alder Lake microprocessors to prevent customers from enabling AVX-512. In older Alder Lake family CPUs with some legacy combinations of BIOS and microcode revisions, it was possible to execute AVX-512 family instructions when disabling all the efficiency cores which do not contain the silicon for AVX-512"
Thank you for this great video.