Subscribed... thank you for delivering this with such energy and enthusiasm. I am a very low level electronics student (level 4/5) (distance learner) and have found much of the content so far very difficult to digest. You have really broken walls here for me. Best regards.
When you calculate the Max Intrinsic Gain of the CB stage, you forgot that as Rs increases, less and less voltage appears across the transistor. Your calculations should include the Rin / (Rin+Rs) term which shrinks as Rs increases, hence the actual intrinsic gain of gm ro.
The active load for a common emitter stage is somewhat strange. It's like connecting two current sources in series which is impossible in circuit theory. It'd make the circuit irregular wouldn't it? How can we still make this? How can we resolve this contradiction? Is it enough to assume that those two current sources have finite resistance?
Its really not, because the current Ic is not equivalent to current source, rather voltage controlled current source, which in reality isnt something that generates, rather something that is generated. So even though in the name says its voltage controlled current source, and we draw it similarly as current source on the circuit schemes, it is just a symbol that we use to represent it. I hope I understood the question and helped!
@@deckosmeker3530 let me rephrase the question then. Can we connect a current source and a voltage controlled current source (and their values of current being different) in series? If so, what will be the common current?
@@MrGyulaBacsi Undrestood. Yes, we can, because, as i said, voltage controlled current source isnt a source in reality, rather symbol for that particular current. If we connect them in series, current will be the current of current source, because the current source forces its current through the circuit in which its connected. Of course, this applies only to DC regime, because in small signal regime all of the voltage and current sources are turned off, and you will be left with only gm•vbe voltage controlled current source that represents ic.
The output resistance is taken into account in both cases (see video 121N). What is being done here is to compare the 'intrinsic' output resistance of the stage that determines its maximum intrinsic gain (beta gm ro) and compare it with the maximum intrinsic gain of the common-emitter (gm ro).
@@AliHajimiriChannel Thank you so much but I still don't understand for emitter degeneration case. I have seem some equation that include ro including in the gain equation. However, how can we proof this?
@Ali Hajimiri Or I should say why the output resistance of common collector configuration is not taken into account for calculating the gain? Thank You
@@AliHajimiriChannel Wouldn't the intrinsic gain for the CE stage with emitter degeneration also follow the same derivation in CB stage and yield Av,max = -gm (Rc // beta*ro)? I'm confused why the beta would only appear for intrinsic gain of CB if the result of R'out was taken from the CE stage with ro and RE.
What would happen if we would to change the Vbe of the top PNP transistor like Vbe of the lower NPN transistor in CASCODE, or have it with inverted phase? Would we get some benefit?
Subscribed... thank you for delivering this with such energy and enthusiasm. I am a very low level electronics student (level 4/5) (distance learner) and have found much of the content so far very difficult to digest. You have really broken walls here for me. Best regards.
Sir the clasa is awesome and concept are very well taught by you please upload the video of other topics as well
When you calculate the Max Intrinsic Gain of the CB stage, you forgot that as Rs increases, less and less voltage appears across the transistor. Your calculations should include the Rin / (Rin+Rs) term which shrinks as Rs increases, hence the actual intrinsic gain of gm ro.
The active load for a common emitter stage is somewhat strange. It's like connecting two current sources in series which is impossible in circuit theory. It'd make the circuit irregular wouldn't it? How can we still make this? How can we resolve this contradiction? Is it enough to assume that those two current sources have finite resistance?
Its really not, because the current Ic is not equivalent to current source, rather voltage controlled current source, which in reality isnt something that generates, rather something that is generated. So even though in the name says its voltage controlled current source, and we draw it similarly as current source on the circuit schemes, it is just a symbol that we use to represent it. I hope I understood the question and helped!
@@deckosmeker3530 let me rephrase the question then. Can we connect a current source and a voltage controlled current source (and their values of current being different) in series? If so, what will be the common current?
@@MrGyulaBacsi Undrestood. Yes, we can, because, as i said, voltage controlled current source isnt a source in reality, rather symbol for that particular current. If we connect them in series, current will be the current of current source, because the current source forces its current through the circuit in which its connected. Of course, this applies only to DC regime, because in small signal regime all of the voltage and current sources are turned off, and you will be left with only gm•vbe voltage controlled current source that represents ic.
@10:44 Should the dependent source (alpha*ie) resistance be included in calculating the output resistance?
Love you professor!
Sir, at the end of the video, why did you say "you lose alpha"? Why the factor of alpha gets lost? thank you
Hello professor how can we get access to the practice problems
Afarin
@ali Hajimiri May I ask why for the gain of common base configuration has to include the output resistance? Why the commom emitter doesn't require?
The output resistance is taken into account in both cases (see video 121N). What is being done here is to compare the 'intrinsic' output resistance of the stage that determines its maximum intrinsic gain (beta gm ro) and compare it with the maximum intrinsic gain of the common-emitter (gm ro).
@@AliHajimiriChannel Thank you so much but I still don't understand for emitter degeneration case. I have seem some equation that include ro including in the gain equation. However, how can we proof this?
@Ali Hajimiri Or I should say why the output resistance of common collector configuration is not taken into account for calculating the gain? Thank You
@@AliHajimiriChannel Wouldn't the intrinsic gain for the CE stage with emitter degeneration also follow the same derivation in CB stage and yield Av,max = -gm (Rc // beta*ro)? I'm confused why the beta would only appear for intrinsic gain of CB if the result of R'out was taken from the CE stage with ro and RE.
What would happen if we would to change the Vbe of the top PNP transistor like Vbe of the lower NPN transistor in CASCODE, or have it with inverted phase? Would we get some benefit?
Lower transistor would act as a load for upper one, that is we would have CS stage with degeneration where Re would be ro of lower transistor.