Who knows C language they can easily learn any other language. If you are good in C then verilog and system verilog will be easy for you to write and understand.
always block includes all the input signals which are sensitive to the always block (hence it's called sensitivity list). If always block execution depends on some input signal then include those signal only. If you leave any required input inside always block then it may cause false hardware. Mux , here you can include s0,S1,i0,i1,i2,i3 if always block execution depends on user input then it needs to be included else NO.
You are best . All your verilog tutorial are easy to understand and very deep . So thanks a lot for sharing your valuable time .
In C there is...
Switch(exp)
Case value: ....
Default:...
But I like verilog sytax now!!
Good explanation
Who knows C language they can easily learn any other language. If you are good in C then verilog and system verilog will be easy for you to write and understand.
Loved your explanation and thanks a lot for this beautiful concept.
sir inside always@( ) we can take only so and s1 as io i1 i2 i3 are changing or it is depending upon the user input also
always block includes all the input signals which are sensitive to the always block (hence it's called sensitivity list). If always block execution depends on some input signal then include those signal only. If you leave any required input inside always block then it may cause false hardware.
Mux , here you can include s0,S1,i0,i1,i2,i3
if always block execution depends on user input then it needs to be included else NO.
These all statements comes under behavior modeling??
Yes, its behavioral modeling.
else if