VHDL Lecture 2 Understanding Entity, Bit, Std logic and data modes
ฝัง
- เผยแพร่เมื่อ 24 มี.ค. 2016
- Welcome to Eduvance Social.
Our channel has lecture series to make the process of getting started with technologies easy and fun so you can make interesting projects and products.
The channel hosts series of lectures to get started with different technologies covering topics like Programmable system on chip (PSoC), ARM mbed, Arduino, FPGA design using VHDL, VLSI design using Electric, Spice modelling using LT spice, PCB designing using Eagle, Robotics and much more to come.
Do like and subscribe to our channel.
Keep learning! Keep Eduvancing!
Thank you sir for such great explanation of vhdl.
Part 1 and part 2 of videos both were helpful! Thankyou :D
Very good explained , thankyou
You r really a very good Teacher....Thanks 4 making such vdos.
thanks man... very well explained👍
thank you sir. very good explanation
Thank u John it was very helpful
Very nice explanationThanks sir
very helpful thanks a lot
very helpful thanks a lot Doctor
Thank you so much Sir...it helped a lot
Thank you Doctor Jonathan Joshi
amazing explanation sir
thank you!!!!
thank you sir
STD_LOGIC: Is there a difference between X and W?
'X' represents a state where the output of that particular signal couldn't be determined because there were two signals(one HIGH and one LOW) driving that output.
'W' represents a state where the output of that particular signal couldn't be determined because there were two ''weak'' signals(one weak HIGH and one weak LOW) driving that output.