This is one of the best CMOS videos I have seen. Thank you so much for making it. Hope you can make more and more like this for different analog blocks.
Hi Susanta, we havent heard you in last 5+ yrs. Please upload more video on latest technology, IC sub block designs etc. Hope we will listen once again.
This video is extremely good and helpful. Your explainations for the concepts are very simple and clear. Thank you so much for taking the time to do this video.
Thank you so much for taking the effort to make those videos. They are the best I have seen to explain two stage OpAmps. I hope you will make more videos in the future.
Thanks a lot for uploading excellent video. A small typo in folded cascode resistance calculation, output resistance should be gm*ro*ro rather than (gm*ro)(gm*ro). It is OK when you calculated voltage gain later. Overall, excellent lectures, please post more of these. Thanks again.
Are you sure about the Green Plot you have shown ? for the close loop bandwidth. Because advantage of -ve feedback is that it increases Bandwidth en.wikipedia.org/wiki/Negative_feedback_amplifier I think 3db bandwidth of close loop will increase compared to open loop. www.analog.com/library/analogDialogue/archives/43-09/Edch%201%20op%20amps.pdf Above shows the correct plot. Once the opamp is in closed loop there is no concept of UGB, it is only bandwidth. You want to mention that OPAMs 3-db BW is increased but operational BW is reduced. Please confirm
Won't the gain of the first stage be what he wrote, divided by two? Only half the input voltage is being translated to the Vo stage, and since there aren't two output v's to make the voltage *2 again, the gain should be divided by 2. Correct?
no, there are two paths for the current to reach Vout. If the loads were resistive, or diode connected NMOSes, it would have been half. The PMOS active loads switch the direction of current flow to allow for the full gain to appear across the output.
To calculate the overall voltage gain, why has the contribution of M1 and M5(acting as active load) not been considered. Sir, isn't the gain Avo you calculated the overall differential gain rather than the DC gain. Correct if me if I am wrong
Your proposal would have been valid if we're to deal with a completely symmetrical structure, i.e. power devices with the same type of loading (be it the resistive or active source loads; here M5 is diode-connected but M6 is not so). Because of the current of M5 is mirrored to M6, we can assume gm of M1 and M2 are equal but gain determined by M1 and M5 is=gm1*rout=gm1/gm5 (determined approximately by the ratio of W/L of these 2 devices) and is small. In such case, we'll consider the gain determined at the high-impedance node (formed by M2-M6 pair) only. It's not completely called as differential gain (since both input structures are not symmetrical). Here inputs are differential; it helps to have rejection of common-mode noise, but gain is basically single ended, determined by high-impedance node. Or if you want to call it a differential gain you can think it as (very high gain determined by M2-M6 pair)- (low gain determined by M1-M5 pair) = gain determined by M2-M6 pair.
at the end of the video, the zero is 1/RC and pole is 2/RC. So, for the closed loop response it should increase +20dB/dec and flatten out at the pole 2/RC due to the -20dB/dec contribution correct? This should cause stability problems if the pole and zero introduced by the feedback is within the bandwidth?
One of the best videos on frequency response of opamps. Highly recommended to watch.
This explanation will never get old. Please keep sharing your design experience with such lectures
Hello Sir ❤ , Please upload more topics in such a lucid way
This is one of the best CMOS videos I have seen. Thank you so much for making it. Hope you can make more and more like this for different analog blocks.
This video is a GEM. The lecture notes look a lot like how Prof. Asad Abidi teaches analog circuits!
Hi Susanta, we havent heard you in last 5+ yrs. Please upload more video on latest technology, IC sub block designs etc. Hope we will listen once again.
This video is extremely good and helpful. Your explainations for the concepts are very simple and clear. Thank you so much for taking the time to do this video.
Thank you Mr. Sengupta. This video really saved me time. Your experience is quite helpful while explaining the noise concept.
Thank you so much for taking the effort to make those videos. They are the best I have seen to explain two stage OpAmps. I hope you will make more videos in the future.
Thankyou susanta
Very Informative Lecture
thanks a lot for this clear and thorough explanation
it was great and helpful. Thank you. Looking forward to seeing more video
Thank you so much for the video sir !! :) Really helped me in understanding the basics of analog integrated circuits better .
Thank you for this, friend. Very nicely done
Thanks a lot for uploading excellent video. A small typo in folded cascode resistance calculation, output resistance should be gm*ro*ro rather than (gm*ro)(gm*ro). It is OK when you calculated voltage gain later. Overall, excellent lectures, please post more of these. Thanks again.
beautifully explained....
Good lecture!
Are you sure about the Green Plot you have shown ? for the close loop bandwidth.
Because advantage of -ve feedback is that it increases Bandwidth
en.wikipedia.org/wiki/Negative_feedback_amplifier
I think 3db bandwidth of close loop will increase compared to open loop.
www.analog.com/library/analogDialogue/archives/43-09/Edch%201%20op%20amps.pdf
Above shows the correct plot.
Once the opamp is in closed loop there is no concept of UGB, it is only bandwidth.
You want to mention that OPAMs 3-db BW is increased but operational BW is reduced.
Please confirm
sorry, but i didn't get how this UGBW calculated...
Won't the gain of the first stage be what he wrote, divided by two? Only half the input voltage is being translated to the Vo stage, and since there aren't two output v's to make the voltage *2 again, the gain should be divided by 2. Correct?
no, there are two paths for the current to reach Vout. If the loads were resistive, or diode connected NMOSes, it would have been half. The PMOS active loads switch the direction of current flow to allow for the full gain to appear across the output.
Best!
To calculate the overall voltage gain, why has the contribution of M1 and M5(acting as active load) not been considered. Sir, isn't the gain Avo you calculated the overall differential gain rather than the DC gain. Correct if me if I am wrong
Your proposal would have been valid if we're to deal with a completely symmetrical structure, i.e. power devices with the same type of loading (be it the resistive or active source loads; here M5 is diode-connected but M6 is not so). Because of the current of M5 is mirrored to M6, we can assume gm of M1 and M2 are equal but gain determined by M1 and M5 is=gm1*rout=gm1/gm5 (determined approximately by the ratio of W/L of these 2 devices) and is small. In such case, we'll consider the gain determined at the high-impedance node (formed by M2-M6 pair) only. It's not completely called as differential gain (since both input structures are not symmetrical). Here inputs are differential; it helps to have rejection of common-mode noise, but gain is basically single ended, determined by high-impedance node. Or if you want to call it a differential gain you can think it as (very high gain determined by M2-M6 pair)- (low gain determined by M1-M5 pair) = gain determined by M2-M6 pair.
at the end of the video, the zero is 1/RC and pole is 2/RC. So, for the closed loop response it should increase +20dB/dec and flatten out at the pole 2/RC due to the -20dB/dec contribution correct? This should cause stability problems if the pole and zero introduced by the feedback is within the bandwidth?