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Susanta Sengupta
เข้าร่วมเมื่อ 4 พ.ย. 2013
RF Analog IC Design
Design example of a CMOS LC VCO (tuning ~ 3 to 6 GHz)
Hi, this is a continuation of the CMOS LC VCO lecture. Before putting a circuit in the simulator, I have tried to capture some simple hand calculations on designing a VCO for a specified tuning range. Here, I take an example of the tuning range to be around 3 GHz to 6 GHz.
Feel free to send any comments or concerns to me at susantasengupta1976@gmail.com
Thanks for watching the video.
Susanta
Feel free to send any comments or concerns to me at susantasengupta1976@gmail.com
Thanks for watching the video.
Susanta
มุมมอง: 29 376
วีดีโอ
Transmit ACPR
มุมมอง 6K9 ปีที่แล้ว
Hi, this is a short lecture on ACPR in transmit chains. Please feel free to submit comments to susantasengupta1976@gmail.com. Thanks for watching the video.
Design example of an 2.4 GHz LNA
มุมมอง 72K9 ปีที่แล้ว
Hi, This is a continuation of the video I published earlier titled "CMOS Narrowband LNA". Thank you all for watching it, your comments and your suggestions. Along those lines, here is a video on how to go about designing an LNA. I have shown some hand calculations that I have used and applied these simple concepts to designing a 2.4 GHz LNA here. The applied steps help one get a good understand...
World phone RFIC transceiver
มุมมอง 7K10 ปีที่แล้ว
Thank you for watching this video. It focusses on how we build cellular RFIC transceivers to support multiple worldwide frequency bands. And, also support multiple standards/modes (latest ones being LTE-Advanced Carrier Aggregation). It also looks briefly as the major blocks used inside the transceivers.
CMOS VCO Design
มุมมอง 48K10 ปีที่แล้ว
Design of CMOS VCOs for cellular/WiFi/Bluetooth and other RFIC applications Oscillator fundamentals. Oscillation frequency, tuning range, phase noise, etc. Noise in the VCO. How does noise in VCO effect Rx or Tx chain performance? Frequency tuning Discrete frequency tuning Continuos frequency tuning Frequency coverage and VCO calibration (in the factory) Supply sensitivity, need for LDO, etc.
RFIC Receiver Passive Mixer
มุมมอง 8K10 ปีที่แล้ว
RFIC Receiver Passive Mixer Passive Mixer architecture Mixer biasing Use of 50% vs 25% duty cycle LO clocks for mixing operation Noise multiplication effect due to low impedance passive mixer 2nd order non linearity (IIP2) of the Mixer
CMOS Narrowband LNA
มุมมอง 28K10 ปีที่แล้ว
CMOS Narrowband LNA LNA Basic ZIF (zero IF) Rx chain Why we need an LNA ? Input Matching Narrowband matching and gain in the matching circuit Design example DC Biasing LNA’s Output load (LC resonant load) Mixer loading on the LNA Noise contributors in the LNA
Cellular RFIC (Rx) System design (part 2)
มุมมอง 4.9K10 ปีที่แล้ว
RF systems Understand various key specifications of the entire Rx chain Gain NF IIP3 IIP2 RSB Design example of an Rx chain over wide input dynamic range (-110 dBm to 0 dBm) Derive switch points, Gain, NF, IIP3, IIP2, etc SNR (signal to noise ratio) ADC swing Do this exercise for signal only and repeat it for various cases of interferers/jammers.
Cellular RFIC (Rx) System design (part 1)
มุมมอง 10K10 ปีที่แล้ว
RF systems Understand various key specifications of the entire Rx chain Gain NF IIP3 IIP2 RSB Design example of an Rx chain over wide input dynamic range (-110 dBm to 0 dBm) Derive switch points, Gain, NF, IIP3, IIP2, etc SNR (signal to noise ratio) ADC swing Do this exercise for signal only and repeat it for various cases of interferers/jammers.
CMOS Opamps
มุมมอง 54K10 ปีที่แล้ว
Two-stage Opamps Classical two-stage opamp NMOS differential input pair with PMOS current mirror load Gain Poles and zeros Concept of stability in a two-pole system Frequency compensation using a Miller capacitor Pole splitting by the Miller capacitor UGBW (Unity gain-bandwidth) and PM (phase margin) RHP (right half plane) zero and use of a nulling resistor Correlation between PM and transient ...
MOS basics
มุมมอง 32K10 ปีที่แล้ว
Fundamentals of MOSFETs Silicon as a semiconductor Si lattice structure “p” type and “n” type Si MOS transistor NMOS and PMOS cross sections MOS as a building block for building analog/RF circuits Physics of turning ON of channel in an NMOS device. Ids - Vds characteristics Active and Saturation regions of operation Drain current equations OFF (leakage) in a MOS device Large-signal and Small-si...
Good lecture
Very good design
Excellent video, when you say active region of the MOSFET are you refering to triode region? Thanks
I think you made a mistake at 17:27 , it should be gm=2/Rp
Thank you very much for the videos Susanta. I tried making excel sheet by my own and really helped me in total understanding of the two videos you posted on LC VCO.
wondering about the 7dB he is adding to ADC op dBm: Pin dBm =10log( (V^2(rms)/R*1000) ) = 10log(Vp^2 * 1000/(2*100) ) = 10log(Vp^2) + 10log(1000/200) = 20log(Vp) + 7dB
at 52:35, why the Av is sqrt(L/C)/50 ?
NF estimation will be 1.6dB
Please make a video on design of Power amplifiers
Hi Susanta, we havent heard you in last 5+ yrs. Please upload more video on latest technology, IC sub block designs etc. Hope we will listen once again.
1:05:29
Thanks your videos -from china
Please do a video on power amplifier design methodology
Hello Sir, I have a doubt. What if we skip the cap bank and use only the mos varactor. How will it affect the circuit?
Very Ex-ordinary work bro. Thank you for your support, bro.
Good lecture suitable for experienced designers
Hello Sir ❤ , Please upload more topics in such a lucid way
What does ACPR stand for?
I watched this over 4 days and it was so much worth it. The intuitive techniques are a necessity when getting lost in long derivations and unable to interpret the results is a reality.
AC ground gets created due to splitting of vin at 3:03:36, i didn't understand?
yes the common node doesnt see any "ac signal" or small signal, in other words even in AC or tran analysis it will remain in the same voltage(= the DC voltage) that you see in the operating point analysis
Thanks for valuable info sir (at free of cost)...Those who are having little bit knowledge about MOSFET , Cadence & Op-amp design ...then they will definitely fall in love with ur teaching ...just like me...
Extremely insightful . Great work
Please could you make more such videos
This explanation will never get old. Please keep sharing your design experience with such lectures
How come cdso is from drain to gate ? Shouldnt it be cgd ?
Also, are you sure the expression you arrive at in 3:39:14 for the zero frequency is correct? Most analyses I've seen of the frequency response of the 5T OTA place the zero at ~ -2gm5/C2; i.e., twice the mirror pole frequency, *and at the LHP*, not RHP.
Dear Sir, thank you for sharing knowledge, and for the excellent method of delivery. Minor notice: From 2:58:16 onwards as you showcase the differential amplifier schematics; it is important to note that your output nodes' polarities should be reversed. Your diff pair devices are still common source amplifiers, so it stands to reason that the polarity of output node at D of device will be of opposite phase to input at G of device.
Very nicely explained sir..
Did you intentionally add this background noise to let people know how important the LNA is?
THANKS FOR SUCH A EXPLANATORY VIDEO......CAN YOU PLEASE suggest or make a video on how to simulate the same design in cadence at 45nm technology.......
can you please tell me when you calculate the Rp you do not enter the unit scale values like (Ghz,nH etc) .what was the reasons.
This video is a GEM. The lecture notes look a lot like how Prof. Asad Abidi teaches analog circuits!
Thank you for sharing your notes and talking through them. So many resources focus on the multitude of possible schematics that the details get disjointed across the entire piece of literature if they are included.
Really clear exposition.
Thanks for the great presentation, very well explained, especially the noise portion!
Is Cgd in parallel with Cgs?
Hi Susanta, these lectures are so great, thanks a lot for you effort, i wish you can post some more videos or please direct me to some material you wrote, like the TX chain maybe some ADC aliasing and other. again thanks you very much
Spectacular.
Extremely Helpful videos. Could you please make a video for transmitter system based design as well?.
thanks a lot for this clear and thorough explanation
Thanks to you and all who make educational videos
please give video how to design this vco In cadence
how to design cap bank in cadence vertuoso software
Sir please provide high frequency (8- 10 gHz) phase locked loop video
Thank you
fantastic video thank you for sharing info
great explanation . thank you sir.
can you please provide the pdf link for the reference . ? i mean hand written pdf .
Hello sir... Can u please mail me the file at 2401.rajni@gmail.com This would be a great help Thanks
Thank you Sir!!! Amazing
Hats off Sir,Simply awesome