The End Is Near: The Problem of PLL Power Consumption - Presented by Behzad Razavi

Abstract - Phase-locked loops (PLLs) play a critical role in communications, computing, and data converters. With greater demands for bandwidth efficiency in wireless systems and higher data rates in wireline transceivers, the maximum tolerable jitter of PLLs has fallen into the sub-100-femtosecond range. Similarly, analog-to-digital converters (ADCs) require extremely low clock jitters as they push for higher resolutions and higher speeds. These trends inevitably raise the PLL power consumption, potentially making it a significant part of the system's power budget. This presentation formulates the jitter-power trade-offs in PLL design, predicting some alarming trends. It is shown that, even if only the VCO power consumption is considered, jitter values falling to a few tens of femtoseconds will translate to watts of power. Moreover, it is observed that PLLs are likely to draw more power than the ADCs that they drive. For example, a 12-bit, 10-GHz ADC will require that the VCO drain more than 3 W for a 3-dB SNR penalty due to jitter. These trends call for innovations in the design of PLLs, crystal oscillators, and ADCs.
Speaker Bio - Behzad Razavi is Professor of Electrical Engineering at UCLA, where he conducts research on analog and RF integrated circuits. An IEEE Fellow, Prof. Razavi has served as an IEEE Distinguished Lecturer and has published more than 200 papers and eight books. He has received eight IEEE best paper awards and four teaching awards, and his books have been published in seven languages. He received the 2012 IEEE Pederson Award in Solid-State Circuits and was recognized as one of the top ten authors in the 50-year history of the IEEE International Solid-State Circuits Conference. He is a member of the US National Academy of Engineering and the recipient of the 2017 IEEE CAS John Choma Education Award.