I wonder what gives you that idea. First of all I'm not involved in dram design, so it's true that I'm guessing and that I don't know for sure. But... if one address can access a data (x4) and it comes from a same array, that means the 4 bits in that array have the same column / row address; in that case, row / column address has lost its meaning. I can't think of a logical explanation for this. So... I'm guessing it's correct that the x4 data comes from 4 arrays.
@@openlogic925 I think I know where the disconnect is. You were using a model to demonstrate the x4 concept whereas I was referring to an actual implementation.
@@openlogic925 I'd also like to add that a page is simply a row. So this also explains why in actual implementations, a bank is 1 big array (instead of viewing a bank as multiple stacked arrays, treat it as as 1 big 2-D array).
Hahaha... That's funnily embarrassing for me 😄. Just when I take a little pride in creating easy-to-understand visual, along came an expert saying I've been telling it wrong . I hope the only mistake is the stacking visual. It should be one array segregated to 4 regions, resembling 4 arrays. Thanks for the info. Though it does shaken me a little, about making guesses in future videos.
@@openlogic925 Hey brother, I am by no means an expert. I merely came across different DDR lectures online and noticed you explained some stuff differently. The model you used to demonstrate the x4 (wide column-width) concept is great for visualizing what's going on under the hood. I appreciate your high quality videos.
Thank you so much for making DRAM concept crystal clear.
You’re very much welcome
Thank you for excellent explanation
You're welcome 😊
I think x4 means 4 bits could be accessed externally at a time within 1 array, not 4 arrays.
I wonder what gives you that idea. First of all I'm not involved in dram design, so it's true that I'm guessing and that I don't know for sure. But... if one address can access a data (x4) and it comes from a same array, that means the 4 bits in that array have the same column / row address; in that case, row / column address has lost its meaning. I can't think of a logical explanation for this. So... I'm guessing it's correct that the x4 data comes from 4 arrays.
@@openlogic925 I think I know where the disconnect is. You were using a model to demonstrate the x4 concept whereas I was referring to an actual implementation.
@@openlogic925 I'd also like to add that a page is simply a row. So this also explains why in actual implementations, a bank is 1 big array (instead of viewing a bank as multiple stacked arrays, treat it as as 1 big 2-D array).
Hahaha... That's funnily embarrassing for me 😄. Just when I take a little pride in creating easy-to-understand visual, along came an expert saying I've been telling it wrong . I hope the only mistake is the stacking visual. It should be one array segregated to 4 regions, resembling 4 arrays. Thanks for the info. Though it does shaken me a little, about making guesses in future videos.
@@openlogic925 Hey brother, I am by no means an expert. I merely came across different DDR lectures online and noticed you explained some stuff differently. The model you used to demonstrate the x4 (wide column-width) concept is great for visualizing what's going on under the hood. I appreciate your high quality videos.