Mock Interview - Part 2, VLSI Design Verification Role

[@ramudukuruva3145]

Nice Keerthi you have good talent you will have bright features in verification domain

[@interviewquestions838]

bro, it is bright future, not bright features

[@ramojireddy8161]

time line 24:00 we can't use for loop and increment is not possible in constraints right

[@munagaldinesh4300]

yes

[@shilpashreeshekar3018]

Can you please increase the quality of this video it's not clearly seen