- 431
- 746 786
Semi Design
India
เข้าร่วมเมื่อ 24 ต.ค. 2015
Semi Design, established in 2014, is a prominent service and training company headquartered in Greater Noida, India. Our core focus lies in providing comprehensive training in VLSI frontend domains, including Design Verification, CMOS Design, DFT, and Static Timing Analysis. Over the years, we have honed our expertise to deliver best-in-class training that aligns with industry standards and prepares our students for successful careers in the semiconductor field.
At Semi Design, our approach is rooted in continuous improvement. We are committed to enhancing our training methodologies to ensure they remain effective and relevant. This commitment is reflected in our use of cutting-edge materials, industry-oriented assignments, mock interviews, and hands-on experiences. These elements not only enrich the learning experience but also equip our students with practical skills that are highly valued in the industry.
At Semi Design, our approach is rooted in continuous improvement. We are committed to enhancing our training methodologies to ensure they remain effective and relevant. This commitment is reflected in our use of cutting-edge materials, industry-oriented assignments, mock interviews, and hands-on experiences. These elements not only enrich the learning experience but also equip our students with practical skills that are highly valued in the industry.
UVM Workshop Day 1 | VLSI Job Oriented Program
UVM Workshop Day 1 | VLSI Job Oriented Program
มุมมอง: 185
วีดีโอ
SoC Design & Verification Program From New Year 2025
มุมมอง 13521 วันที่ผ่านมา
🎉 Kickstart Your New Year with SoC Design & Verification Expertise! 🎉 New Year, New Skills, New Opportunities! 🚀 We are thrilled to announce the New Year Batch of our flagship 10-Week SoC Design & Verification Program-an online, industry-driven training designed to help you build your career in semiconductors. Know More About This Program In Just Seconds: lnkd.in/dry7JzD 🌟 Why Join This Program...
New Era of Transistors In Semiconductors
มุมมอง 9121 วันที่ผ่านมา
🌟 The New Era of Transistors in 3D Chips | Revolutionizing Semiconductors 🌟 Welcome to the future of semiconductor technology! In this video, we explore the new era of transistors and their transformative role in 3D chip designs. 📌 Key Topics Covered: 🔹 What are 3D chips? 🔹 The evolution from planar transistors to 3D structures 🔹 Benefits of 3D transistors in performance and power efficiency 🔹 ...
Adder SystemVerilog | Design & Verification Training
มุมมอง 26121 วันที่ผ่านมา
🚀 SystemVerilog Adder Implementation Tutorial In this video, we dive into the implementation of an adder using SystemVerilog, a powerful hardware description and verification language. Whether you're preparing for semiconductor job interviews or looking to enhance your hardware design skills, this tutorial will help you: ✔️ Understand adder design concepts ✔️ Write and simulate SystemVerilog co...
Master SystemVerilog Randomization | Comprehensive Guide
มุมมอง 15321 วันที่ผ่านมา
Master SystemVerilog Randomization | Comprehensive Guide Description: Unlock the power of SystemVerilog Randomization with this comprehensive guide! In this video, we cover: ✅ What is randomization in SystemVerilog? ✅ Randomization techniques for verification. ✅ Constraints and constraint solving. ✅ Practical examples of random variables. ✅ Debugging randomization issues. Enhance your verificat...
SystemVerilog Randomization Part 2
มุมมอง 12728 วันที่ผ่านมา
Discover why randomization in SystemVerilog is a game-changer for modern verification. Learn how constrained randomization helps create robust, efficient test environments to uncover edge cases and enhance coverage. Perfect for beginners and verification enthusiasts! Don't forget to like, share, and subscribe for more insights. #SystemVerilog #Randomization #Verification
SystemVerilog Randomization Part 1
มุมมอง 337หลายเดือนก่อน
TH-cam Description: Unlock the power of randomization in SystemVerilog! 🎲 In this video, we dive deep into constrained randomization, randomize() method, and constraint-solving techniques to simplify your verification process. Learn how SystemVerilog helps you create efficient and reusable testbenches by generating dynamic and unpredictable stimulus. 💡 Key Topics Covered: • Basics of Randomizat...
Advanced Verification Workshop Session 1 - #systemverilog #vlsitraining @SemiDesign
มุมมอง 5822 หลายเดือนก่อน
Advanced Verification Workshop Session 1 - #systemverilog #vlsitraining @SemiDesign
Systemverilog Coverage & Assertion Verification @SemiDesign
มุมมอง 6352 หลายเดือนก่อน
Systemverilog Coverage & Assertion Verification @SemiDesign
Verilog HDL - Coding Tips #vlsitraining #vlsidesign #verilog #semiconductor
มุมมอง 4973 หลายเดือนก่อน
Verilog HDL - Coding Tips #vlsitraining #vlsidesign #verilog #semiconductor
Mock Interview - Digital Electronics #vlsi #vlsitraining #vlsidesign #digitalelectronics
มุมมอง 5703 หลายเดือนก่อน
Mock Interview - Digital Electronics #vlsi #vlsitraining #vlsidesign #digitalelectronics
System Verilog - VLSI Training institution
มุมมอง 6773 หลายเดือนก่อน
System Verilog - VLSI Training institution
GITHUB & Resume Guide - Top VLSI Institution
มุมมอง 4103 หลายเดือนก่อน
GITHUB & Resume Guide - Top VLSI Institution
ASIC Design & Verification - Job oriented Program Live sessions | Top VLSI Institution @SemiDesign
มุมมอง 3814 หลายเดือนก่อน
ASIC Design & Verification - Job oriented Program Live sessions | Top VLSI Institution @SemiDesign
ASIC Design & Verification Job Oriented Program Session 1 #vlsi #semiconductor #technology #fpga
มุมมอง 9814 หลายเดือนก่อน
ASIC Design & Verification Job Oriented Program Session 1 #vlsi #semiconductor #technology #fpga
AMBA APB CODE | #VLSI Training & Projects #systemverilog #uvm #semiconductorindustry
มุมมอง 1.6K5 หลายเดือนก่อน
AMBA APB CODE | #VLSI Training & Projects #systemverilog #uvm #semiconductorindustry
VLSI Protocols Workshop | i2c Protocol Code Explanation
มุมมอง 1.1K5 หลายเดือนก่อน
VLSI Protocols Workshop | i2c Protocol Code Explanation
VLSI PROTOCOLS WORKSHOP | #vlsi #workshop #semiconductor #systemverilog #uvm #verilog #verification
มุมมอง 3336 หลายเดือนก่อน
VLSI PROTOCOLS WORKSHOP | #vlsi #workshop #semiconductor #systemverilog #uvm #verilog #verification
PCIe Protocol Demo Session #pcie #pcie4 #vlsi #vlsitraining
มุมมอง 2.8K6 หลายเดือนก่อน
PCIe Protocol Demo Session #pcie #pcie4 #vlsi #vlsitraining
APB Protocol From Scratch Part 4 | Protocols Basics | #vlsi #vlsitraining #verilog
มุมมอง 1.1K7 หลายเดือนก่อน
APB Protocol From Scratch Part 4 | Protocols Basics | #vlsi #vlsitraining #verilog
APB Protocol From Scratch Part 3 | Protocols Basics | #vlsi #vlsitraining #verilog
มุมมอง 9597 หลายเดือนก่อน
APB Protocol From Scratch Part 3 | Protocols Basics | #vlsi #vlsitraining #verilog
APB Protocol From Scratch Part 2 | Protocols Basics | #vlsi #vlsitraining #verilog
มุมมอง 1.4K7 หลายเดือนก่อน
APB Protocol From Scratch Part 2 | Protocols Basics | #vlsi #vlsitraining #verilog
APB Protocol From Scratch Part 1| Protocols Basics | #vlsi #vlsitraining #verilog
มุมมอง 4.8K7 หลายเดือนก่อน
APB Protocol From Scratch Part 1| Protocols Basics | #vlsi #vlsitraining #verilog
AXI Protocol Basics | Prepare For VLSI Industry | Join Our Advance Verification Program
มุมมอง 3.8K7 หลายเดือนก่อน
AXI Protocol Basics | Prepare For VLSI Industry | Join Our Advance Verification Program
SystemVerilog Assertions From Scratch | Crack VLSI Interview #vlsi
มุมมอง 3.6K7 หลายเดือนก่อน
SystemVerilog Assertions From Scratch | Crack VLSI Interview #vlsi
SystemVerilog Basics From Scratch Part 2
มุมมอง 5627 หลายเดือนก่อน
SystemVerilog Basics From Scratch Part 2
SystemVerilog Basics From Scratch Part 1
มุมมอง 8337 หลายเดือนก่อน
SystemVerilog Basics From Scratch Part 1
hi could you please share the notes pdf
CPU is dead
Welcome to popcorn ! Where is profile for reballing ? LoL
Thats what happens, when you let ai generate a clip out of trash video snipets, zero logic. first he remove a cpu from a burned mainboard. without that info, no one will understand why.
WTF
なんやねん。この葬式みたいな音楽は。
Could you share me this materials, please?
@@ngocmanprocoder yes
Why are there so many questions in the Comments?
For array representation
I guess?
Where’s the disassembly? I saw someone re-balling the chip to put it back onto the logic board.
Ok... and then?
Bro why you removed it😅
normal re-balling chip
3rd xnor
Please when you are explaining tell the audience to turn off their microphones, they can open it just when they need to ask a question not to react to every word you say, thanks for this explanation it’s insightful 👍🏻
Xnor
Xnor
PLEASE CAN YOU SHARE PDFS.
Madam good afternoon madam Can u help by giving any ppt for system verilog madam
Xnor
XNOR
40:41 seems like a nightmare to me. Directed,regression,unit testcases
C option
XNOR
You are restricting the size to 30. Lets assume size is 100 then? I got the answer for it. Use the below constraint constraint c_num{ foreach(data[i]) if(i%2==0) data[i] == 0; else if(i==1) data[i] == 1; else if(data[i-2]==9) data[i]==1; else data[i] == data[i-2]+1; }
where is part 2
there is no sound
Hi semidesign, It is usually not a good idea to drive the full and empty output logic combinationally and assigned to the final output. When there is a push and the current wptr is MAX-1, then it will go to MAX value. You can check this condition and pass it through a flop. The output of the flop is full. Same for empty. This way the final full and empty signals come from flops which greatly reduces output delay.
Iam Interested to apply
When will next uvm workshop madam......
uart can configure as half duplex or full duplex as well
Mam how to contact to you for mock interviews
can i know what is the purpose of this signal in baudrate_generator sel[1:0] ; and also i get code from you please share code
when is event scheduled ?
Thank You mam Nice lecture
Nice presentation with good content
Ma'am please share that PDF
"very easy explanation"
💯💯💯
What's this song!?!
Bro thats small to an ant
Xnor
Mam,if we have three 32-bit inputs, is the number of possible combinations be (((2^32)^(2^32))^(2^32)) mam?
PLEASE CAN YOU SHARE PDFS.
XNOR