How hard is it to use an FPGA for compute acceleration in 2023?

Speaker: James C. Hoe, Carnegie Mellon University
In this talk I want to explore the question: how hard is it to use an FPGA in a computer system in 2023? Secondarily, there is the question: what application domain would most profit from FPGA acceleration if the historical programmability and usability challenges are removed. With advances in new single-source heterogeneous programming languages and high-level synthesis, I will argue that using an FPGA for compute acceleration is no harder than using a GPU through CUDA/OpenCL (which is by no means easy). Applying Intel DPC++/oneAPI to an interesting design example in high-throughput, low-latency streaming data analytics (i.e., aggregation), I will show that (1) we shouldn't automatically expect a loss of quality when using HLS to design for FPGAs; and, more importantly (2) the resulting HLS IPs can be much more maintainable and reusable, as well as being more accessible to application-level experts to assemble new streaming application pipelines. With an improved systematic programming flow, data stream processing---including online and offline transformation, inspection, and analytics---is one of the prime candidates to leverage FPGAs’ advantage over CPU/GPU/ASIC options in a computer system.
Speaker Bio: James C. Hoe is a Professor of Electrical and Computer Engineering at Carnegie Mellon University. He received his Ph.D. in EECS from Massachusetts Institute of Technology in 2000 (S.M., 1994). He received his B.S. in EECS from UC Berkeley in 1992. He is interested in many aspects of computer architecture and digital hardware design, including the specific areas of FPGA architecture for computing; digital signal processing hardware; and high-level hardware design and synthesis. He is a Fellow of IEEE. For more information, please visit www.ece.cmu.edu....
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