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did I hear that right, mr. presenter? you did this project while working at Intel? And you were not using Intel/Altera FPGAs but Xilinx. Why???? As a former Altera/Intel manager in the FPGA group I feel disappointed :)

Excellent!! Is there a technical report following this? Would l9ve to dive into the details and try to reproduce some results

Imagine that you have 3 binary files, each represent a FPGA binary for different DNN models. Then you have an FPGA. Instead of making hardware architecture universal that could support all 3 DNN models, like GPU or ASIC, you could just optimize each DNN model for FPGA via software codesign, and reprogram the FPGA on the fly, such that 3 of the DNN models has distinctive hardware optimization. Now the FPGA has the same flex as ASIC yet cost way less space and money. This is where the fun begins.

If you knew the fundamental difference in area, speed and power of an FPGA vs ASIC, why not just focus on the key architectural improvements and make an ASIC? Surely, Intel would be able to do so?

Sing song la de da.

Hi Mohamed, I'm a beginner at AI and deep learning. And I have just started to learn these things. In order to build some deep learning hardware applications/IPs for practice and hands on purpose. I'm really fascinated with the things that AI can do in field of health monitoring and medical diagnostics. I'll be really grateful and happy if you can provide me your mail id. I would like to keep in touch with you for guidance and mentorship. Thanks

The 90's called they want their mic back.

🎯 Key Takeaways for quick navigation: 00:00 📅 *Introduction to FPGA and Deep Learning* - FPGA's initial attempt in deep learning in 2016. - Comparison to GPUs and the development of deep learning accelerators. - Overview of FPGA's early optimization strategies. 10:00 🧠 *Challenges and Competition from GPUs* - The rapid evolution of GPUs in deep learning with low precision arithmetic. - FPGAs falling behind ASICs and GPUs in performance. - The limitations of FPGA customization and adaptability. 20:00 🔄 *Exploring Future Possibilities for FPGAs in Deep Learning* - The concept of co-design in deep learning hardware and software. - Advocating for a flexible approach to optimizing both hardware and neural network architecture. - The potential of automated machine learning for FPGA-based deep learning. 20:46 🧠 *Automated Machine Learning and Neural Architecture Search* - Different deep neural networks (DNNs) can perform the same task. - Automated machine learning and neural architecture search are common practices in industry. - FPGAs offer the ability to customize both neural network architecture and hardware parameters simultaneously, leading to better performance. 28:09 ⚙️ *Logic Neural Networks and Logic Shrinkage* - Logic neural networks involve transforming DNNs into circuits using look-up tables (LUTs). - Logic shrinkage optimizes circuit netlists for FPGA implementation, resulting in higher efficiency. - Fine-grained pruning and training in the LUT domain can lead to significant FPGA area efficiency improvements. 36:00 🖥️ *FPGA DLA Devices and End-to-End Deep Learning Workloads* - Deep learning workloads are heterogeneous and consist of more than just DNNs. - Accelerating the entire end-to-end deep learning workload, including pre-processing and post-processing, is essential. - Optimizing system architecture for hardware acceleration beyond DNNs is necessary for overall performance improvements. 42:33 🚀 *FPGA's role in deep learning acceleration* - FPGA's suitability for accelerating deep neural networks (DNNs). - The importance of reconfigurable hardware in data centers. 45:32 🔄 *Hybrid FPGA-DLA devices for heterogeneous workloads* - The need for hybrid FPGA-DLA devices for heterogeneous workloads. - Implementing custom pre-processing and post-processing on FPGAs. - Research questions and challenges in developing these hybrid devices. 50:18 🌐 *Embedded Networks-on-Chip (NoC) for FPGAs* - Introduction to Embedded Networks-on-Chip (NoC) for FPGAs. - Solving FPGA designer challenges in system-level interconnects. - Benefits and efficiency of using an embedded NoC in FPGAs. 53:21 💡 *Using NoC-enabled FPGAs for pre and post-processing in deep learning* - Leveraging NoC-enabled FPGAs for pre and post-processing in deep learning workloads. - Connecting efficiently to deep learning accelerators. - The potential of FPGA devices in accelerating deep learning applications. Made with HARPA AI

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Very interesting and clearly presented!

Where can I download this presentation PPT?

Software defined data movement is a great way to put it

If I could clap virtually, I would stand up and clap in the end. what an amazing presentation and interesting topic. thank you for sharing this video!

The presentation was extraordinary!! I am a student at the university of Stuttgart as well and this post randomly came across my feed.

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Please can u help me in XSG matlab by fpga

"If you can build it in ASIC, it won't be competitive on an FPGA" So what can't be built in ASIC? Actually, this has been know for a long long time

Awesome work! Thanks for the talk.

Thanks for the talk Mr. Abdelfattah. Is there any course / training to learn these stages of custom h/w kernel development for deep learning ? I am also in a similar field, and my approach is simply to import the hardware from the Synthesizing tool, like Vitis HLS. I am intrested in defining or tweeking some paramteres to make a more customized hardware.

Great presentation. Thanks a lot for sharing. Is the Intel project publicly available ?

Loved the talk!👏 Some very cool ideas!