I2C read is a bit confusing at 8:26. How a slave know which register data it is sending. Isn't it the master needs to first 1. master write slave address 2. master sends register address which it wants to read (rw bit don't care) 3. repeated start with slave address with read bit 1 3. slave started feeding data from that register. Is it correct? I am telling from bma220 datasheet.
Yes. It has a different little more complicated protocol than this typical system. 1. Master sends start bit 2. master sends slave address(7bit) 3. Master sends write condition 4. Slave send ACK master sends register address that required to read(8 bit/LSB ignored = 1 or 0) 4. Slave sends ACK 5. Master send Sr(Repeat start) condition 6. Master send slave address again 7. ACK from slave 8. Slave send 1st data byte 9. ACK from master - Repeat 8/9 for 5 times 10. Slave send last(6th) data byte 11. NACK by master 12. Master sends Stop Clearly explained in this datasheet image.dfrobot.com/image/data/SEN0168/BMA220%20datasheet.pdf
02:00 So if the clock remains high, and some device pulls the data line down (signaling start), and then releases it back to high (signaling stop), would it mean an "empty packet" with no address nor data inside? Is such thing allowed to happen? 03:46 So if I flip the data line _during_ clock high, it would either mean STOP or (RE)START, am I right? 04:40 What if the sender haven't released the data line yet, and the receiver pulls it down too? 08:43 So how can the master inform the slave that it didn't get the last byte correctly?
Agree, SCL, SDA sound the same. Just call it clock and data. There's no error correction. ACK just means "hello, yes I'm here" but doesn't repeat back to the master? I'm correct?
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I2C read is a bit confusing at 8:26.
How a slave know which register data it is sending. Isn't it the master needs to first
1. master write slave address
2. master sends register address which it wants to read (rw bit don't care)
3. repeated start with slave address with read bit 1
3. slave started feeding data from that register.
Is it correct? I am telling from bma220 datasheet.
Yes. It has a different little more complicated protocol than this typical system.
1. Master sends start bit
2. master sends slave address(7bit)
3. Master sends write condition
4. Slave send ACK
master sends register address that required to read(8 bit/LSB ignored = 1 or 0)
4. Slave sends ACK
5. Master send Sr(Repeat start) condition
6. Master send slave address again
7. ACK from slave
8. Slave send 1st data byte
9. ACK from master
- Repeat 8/9 for 5 times
10. Slave send last(6th) data byte
11. NACK by master
12. Master sends Stop
Clearly explained in this datasheet
image.dfrobot.com/image/data/SEN0168/BMA220%20datasheet.pdf
well this is very useful than datasheet i found thx alot
02:00 So if the clock remains high, and some device pulls the data line down (signaling start), and then releases it back to high (signaling stop), would it mean an "empty packet" with no address nor data inside? Is such thing allowed to happen?
03:46 So if I flip the data line _during_ clock high, it would either mean STOP or (RE)START, am I right?
04:40 What if the sender haven't released the data line yet, and the receiver pulls it down too?
08:43 So how can the master inform the slave that it didn't get the last byte correctly?
Nice, good work gentlemen
Is it possible to provide us a means to download this presentation for quick reference?
Thanks!
thanks
nice.. thanks
wow!
A little audio processing would really help. Normalize the level, a tad of compression maybe, and smooth out the freq. response.
Agree, SCL, SDA sound the same. Just call it clock and data. There's no error correction. ACK just means "hello, yes I'm here" but doesn't repeat back to the master? I'm correct?
@@johnborrell9021 No it says "yeah, I received and understood what you sent, send again I am ready"
i fell asleep