@@autohmae I don't see Raspberry Pi itself switching to RISC-V at any time in the near future, but I wouldn't be surprised if they'll offer a HAT with a little RISC-V CPU to play with...
@@GeoStreber My thinking at the moment is: Raspberry Pi Foundation is probably interested in the open source peripherals work RISC-V is trying to get into. This means long term: no more 30 different kinds of ISAs on a single motherboard/CPU combination (on a regular laptop PC their are lots of small chips and even embedded chips inside CPUs which are even running on other ISAs). But all of them move to the same ISA, RISC-V, initially not the CPU.
RV32I is small enough for ASIC designs. Reduced number of registers provides not much benefits for ASIC designs. RV32E could prove useful for FPGAs. Here, registers could be implemented in block ram. Required is a "compressed only; 16bit-only" instruction set with compiler support. This might or might not go hand in hand with a reduced number of registers in order to enable reduced bit widths of instructions. The "compressed only" instruction set might consist of current C instructions. An option with 16bit data bus should provide the same results as 32 bit data bus with 16bit data types. In particular, the binary code of the compiler should be identical.
Is there a chance anyone will develop backdoor free soc? Afaik its open isa but when it comes to production how can we be sure there is no backdoor made in cpu or other components?
I hope affordable RISC-V general purpose computers come soon. We need little kids hacking on these things.
Raspberry Pi foundation is a RISC-V member I think
@@autohmae I don't see Raspberry Pi itself switching to RISC-V at any time in the near future, but I wouldn't be surprised if they'll offer a HAT with a little RISC-V CPU to play with...
@@GeoStreber My thinking at the moment is: Raspberry Pi Foundation is probably interested in the open source peripherals work RISC-V is trying to get into. This means long term: no more 30 different kinds of ISAs on a single motherboard/CPU combination (on a regular laptop PC their are lots of small chips and even embedded chips inside CPUs which are even running on other ISAs). But all of them move to the same ISA, RISC-V, initially not the CPU.
thank you !
Thank a lot.
Thank you for a wonderful state of the union status update! ❤️ from Israel.
RV32I is small enough for ASIC designs. Reduced number of registers provides not much benefits for ASIC designs.
RV32E could prove useful for FPGAs. Here, registers could be implemented in block ram.
Required is a "compressed only; 16bit-only" instruction set with compiler support. This might or might not go hand in hand with a reduced number of registers in order to enable reduced bit widths of instructions. The "compressed only" instruction set might consist of current C instructions.
An option with 16bit data bus should provide the same results as 32 bit data bus with 16bit data types. In particular, the binary code of the compiler should be identical.
wow, it's an Open Source Hardware Revolution :-D !
especially nVidia adopting it, watch out AMD !
Nvidia is very hostile against open source. They refuse to release gpu driver source code. Both Intel and AMD provide open source gpu drivers.
He said in the intro, RISC-V is an open spec. That doesn't directly mean open source. It allows for open source or proprietary implementations.
If something is commercial is much less interesting than if it is free or proprietary. And the latter distinction is a question of the license alone.
Is there a chance anyone will develop backdoor free soc? Afaik its open isa but when it comes to production how can we be sure there is no backdoor made in cpu or other components?
pretty much impossible