U3 L6 | Ring counter | 4 Bit Ring Counter | Shift Register Counter | MOD 4 Ring Counter

#digitalelectronics
#digitalsystemdesign
#dsd
#counter
ring counter using D flip flop
In ring counter output of last flip flop fed back to the input of first flip flop.
in this at a time only one flip flop is in set state.
an n bit ring counter can count n different states only.

[@vinaybalogi2842]

Ma'am I was really stressed out regarding my digital concepts
Thank you for explaining in so much better way and making us understand the concept.
I watched mod 10 synchronous counter and mod 6 synchronous counter. Beautifully explained.
Now I'm here to understand Mod 4 ring counter.
Thank you ma'am 🙏

[@TechnoTutorials2783]

Thanks dear for valuable feedback

[@sandipsinha2537]

Thnk you soo much for this valuable lecture.

[@TechnoTutorials2783]

😊

[@anupgalpalliwar876]

What is CLR

[@TechnoTutorials2783]

Cleared is asynchronous input is used to clear the flip flop means if this is active then flip flop.hold 0

[@B.techPsitWallah]

Thank you mam

[@anupgalpalliwar876]

Mam iske liye basic knowledge konsa laghta hain thoda thoda samja bs .....

[@TechnoTutorials2783]

Serial in serial out shift register