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If we reset at 6 C=1 and B=1 yet A=0. The NAND function is required as these particular devices have active-low set and reset pins (Logic zero makes them happen). If the set and reset pins were active-high, we would use an AND gate :)
Design a Synchronous Mod-6 counter using clocked D Flip-flops to realize the given counting sequence 010, 001, 010, 111, 110, 101. Draw the 'State diagram'. Show the 'Application table for D Flip-flop'. Workout the 'Excitation table' to realize the random counting sequence given. Generate the minimal sum logical expressions for Flip-flop inputs. Implement the relevant logic circuit of Mod-6 counter designed. Plz send this question answer plzz
Hello Friends
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A very short and precise presentation! Smart
Asynchronous counter chala baga cheppav darling ❤️
Thank You Madam❤️
mam how to do the circuit diagram using k map like how we do in synchronous counter?In here i not understood why nand gate is used..
For asyn we don't need any k map
Very simple and clear..
Mam ek doubt .. tum asychronous me baath ke kaya..??? Mere text book me individual input hai .
Super understandable
Nice explanation mam....
Well explained mam
U r video is lot of useful for me
Thankyou for the appreciation and hope this video has helped you.
For much easier learning I would suggest you to go through this link bit.ly/353lpP2 and download the Ekeeda-The Learning Application.You can also
share this with your family and friends.
it is a mod 6 counter ..shouldnt you take 6 values from 0-5 and not 7 values
Dunno if it's late but I think she has to take the value 6 to give clear. So you are right and she is actually taking values from 0-5.
6 is not considered there👍🏻
Thanks for your video, teacher!
Positive triggering mein kya difference hoga
Thank You so much Mam
Thanks 😊👍
Mod 6 asynchronous or make a 6bit asynchronous is same or not?
Hello
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Not same
sorry can you explain, why NAND-Gate is needed?
If we reset at 6 C=1 and B=1 yet A=0. The NAND function is required as these particular devices have active-low set and reset pins (Logic zero makes them happen). If the set and reset pins were active-high, we would use an AND gate :)
Design a Synchronous Mod-6 counter using clocked D Flip-flops to realize the given counting sequence 010, 001, 010, 111, 110, 101. Draw the 'State diagram'. Show the 'Application table for D Flip-flop'. Workout the 'Excitation table' to realize the random counting sequence given. Generate the minimal sum logical expressions for Flip-flop inputs. Implement the relevant logic circuit of Mod-6 counter designed.
Plz send this question answer plzz
Thanks mem helpfull video
Evaru cheppina artham kale honey voice tho sweet ga cheppav
Thankyou
(2^n)-1
n=3
Maximum count is 6
How?????????
6 is 110, and the count for 3 bit can go upto 111, hence n=3
❤
C ko pehle kyun likha
worst explanation
Totally wrong
It's correct explanation.
If you're not interested then you need not to watch it but you should not leave a negative comment like this
xza
Wrong one
thank you very much ma'am