Thank you for the great video. I was wondering if you could explain why the K factor increases as the frequency goes up? Also, when designing a PA (Power Amplifier) that operates at high frequencies (e.g., 28 GHz), does the K factor need to exceed 1 across the entire frequency range, or is it sufficient for it to exceed 1 only near the target frequency?
@@PADAKMON91 K factor and U factor should be checked for stability purposes, these parameters are function of S parameters, since the S21 reduces by increasing the frequency, and K is inversly proportional to S21, that is why by increasing the frequency K factor goes up. Yes can check the K factor at your desired frequency, and it would be enough.
@@profhalimboutayeb Thank you, Prof. Halim! Since this is my first time designing PA, I have some basic questions. I understand that the load pull simulation is done to find the maximum PAE or POWER impedance. After running the load pull simulation, I obtained the value of ZL (18+j19.4) on the left( 12:00 ). Is this the value that I conjugate and use for input matching( 14:32 )? Also, where can I find the impedance( 12:00 ) for output matching( 30:25 ) during the simulation?
@PADAKMON91 Yes, both input and output impedances are extracted from load pull simulation should be conjugated, in load pull simulation the impedance that is calculated in the left windows is used for load matching. For source matching impedance, there are two ways, first in the main schematic of load pull simulation you can set the source impedance and this is the impedance that can be used for source impedance. Or you can set another simulation as a source pull simulation like the one that you did for load-pull. In this case the cakculated parameters in left windows are for source impedance
Thank you, Prof. Halim. Your tutorial videos are very helpful. I would like to ask one question: Is it okay to connect VDD directly to the transistor without using a resistor first? I am planning to design a power amplifier project using fixed bias for the DC biasing, so I am a bit confused about the DC bias design.
@@dittanur5073 In order to separate the DC network from the rf part we need to connect the DC sources to the gate and drain terminals through a RF choke, but in the gate side in order to make sure about the stability, a resistor also should be connected between DC and gate terminal. Connecting the DC to the transistor directly can lead to oscillation and damage the transistor.
@@profhalimboutayebThank you, Prof. Halim, for the explanation. So, it is okay not to use a resistor on the drain side, correct? In previous research, there was an instance where a resistor was used on the drain side, but it overheated and had to be replaced repeatedly. So I want to make sure about this before implementing it on the PCB.
@@dittanur5073 Yes, since the current that is passed through the drain is high, if we put a resistor in drain, it is overheated. So it is not practical. Just a resistor in gate is enough to stabilize the circuit.
I have long been searching for guidance to deepen my expertise in circuit design, particularly in RFICs. Despite extensive efforts to find tutorials on designing RF power amplifiers for CMOS technologies such as 40nm, 56nm, and 45nm, I have only been able to acquire a basic understanding of schematic design. However, I still lack knowledge in creating layouts and performing EM simulations. I am hopeful that, with your expertise, I can gain the knowledge and direction I have been seeking to advance my skills in this field.
@@yassinabdullah5209 Unfortunately, now we do not have access to cadence layout and the transistor stack up, that are used for power amplifier design in CMOS. Maybe later.
It depends on frequency you are going to work, but MW6S004NT11 from NXP is a wideband and 4 watt transistor is a good choise that can be tuned to have 2 watt at the output. CGH4006 from cree , or there are some other transistors from ampleon that based on your frequency can be chosen
Hello Prof, thanks for the great video tutorial. I have a question: in the final layout results, S11 and S22, which represent return loss, is it okay if their values are not < -10 in this power amplifier design case?
@@canopuscapellavega Thank you for your support. Yes, there is always a trade-off between all parameters. As long as we can achieve the desired gain, PAE, and Psat, we do not need to worry about S11. We have applied a 50-ohm termination at the input, so these results were obtained under this condition. If you want to improve the return loss, you can adjust the matching network, but this may sacrifice other parameters.
It does not need a license, you can get the transistor model for ADS from Ampleon website and add it to the ADS as a library. In Design kit menu in the main page, there is an option that can be used for adding the transistor model.
Merci beaucoup Prof. Halim; S'il vous plait, vous pouvez faire complete vidéos concernant design des circuits RF par ADS avec votre explications? depuis les bases au design avancée, ceci ils sera vraiment magenifique. On a besoin trés beaucoup comme cette contenu qui est rare...
Merci beaucoup pour supporter cette chaine TH-cam et pour vos recommendations. Je vais continuer à partager des vidéos tutoriel de conceptions RF, des bases aux circuits avancées.
thank you professor halim. Can I redesign with cascade 2 stage power amplifier with this transitor. What parameter value need resimulate, ex. Loadpull,.... Thank you!
Yes you can do it, as long as you do the matching to 50 ohm. But if you want to cascade, this transistor is going to be last stage. All parameters will be the same and you do not need to change them. But for your first stage, you need to do the load pull simulation again and extract the related parameters accordingly.
RF Rectifier Design Using ADS:
th-cam.com/video/JyvFfPzmjtY/w-d-xo.htmlsi=ejZyr_tF4PNdrUUU
Thank you for the great video.
I was wondering if you could explain why the K factor increases as the frequency goes up? Also, when designing a PA (Power Amplifier) that operates at high frequencies
(e.g., 28 GHz), does the K factor need to exceed 1 across the entire frequency range, or is it sufficient for it to exceed 1 only near the target frequency?
@@PADAKMON91 K factor and U factor should be checked for stability purposes, these parameters are function of S parameters, since the S21 reduces by increasing the frequency, and K is inversly proportional to S21, that is why by increasing the frequency K factor goes up. Yes can check the K factor at your desired frequency, and it would be enough.
@@profhalimboutayeb
Thank you, Prof. Halim!
Since this is my first time designing PA, I have some basic questions.
I understand that the load pull simulation is done to find the maximum PAE or POWER impedance.
After running the load pull simulation, I obtained the value of ZL (18+j19.4) on the left( 12:00 ).
Is this the value that I conjugate and use for input matching( 14:32 )?
Also, where can I find the impedance( 12:00 ) for output matching( 30:25 ) during the simulation?
@PADAKMON91 Yes, both input and output impedances are extracted from load pull simulation should be conjugated, in load pull simulation the impedance that is calculated in the left windows is used for load matching. For source matching impedance, there are two ways, first in the main schematic of load pull simulation you can set the source impedance and this is the impedance that can be used for source impedance. Or you can set another simulation as a source pull simulation like the one that you did for load-pull. In this case the cakculated parameters in left windows are for source impedance
Thank you, Prof. Halim. Your tutorial videos are very helpful. I would like to ask one question: Is it okay to connect VDD directly to the transistor without using a resistor first? I am planning to design a power amplifier project using fixed bias for the DC biasing, so I am a bit confused about the DC bias design.
@@dittanur5073 In order to separate the DC network from the rf part we need to connect the DC sources to the gate and drain terminals through a RF choke, but in the gate side in order to make sure about the stability, a resistor also should be connected between DC and gate terminal. Connecting the DC to the transistor directly can lead to oscillation and damage the transistor.
@@profhalimboutayebThank you, Prof. Halim, for the explanation. So, it is okay not to use a resistor on the drain side, correct? In previous research, there was an instance where a resistor was used on the drain side, but it overheated and had to be replaced repeatedly. So I want to make sure about this before implementing it on the PCB.
@@dittanur5073 Yes, since the current that is passed through the drain is high, if we put a resistor in drain, it is overheated. So it is not practical. Just a resistor in gate is enough to stabilize the circuit.
I have long been searching for guidance to deepen my expertise in circuit design, particularly in RFICs. Despite extensive efforts to find tutorials on designing RF power amplifiers for CMOS technologies such as 40nm, 56nm, and 45nm, I have only been able to acquire a basic understanding of schematic design. However, I still lack knowledge in creating layouts and performing EM simulations.
I am hopeful that, with your expertise, I can gain the knowledge and direction I have been seeking to advance my skills in this field.
@@yassinabdullah5209 Unfortunately, now we do not have access to cadence layout and the transistor stack up, that are used for power amplifier design in CMOS. Maybe later.
can u suggest an amplifier which we can use to design a 2 watt
power amplifier
It depends on frequency you are going to work, but MW6S004NT11 from NXP is a wideband and 4 watt transistor is a good choise that can be tuned to have 2 watt at the output. CGH4006 from cree , or there are some other transistors from ampleon that based on your frequency can be chosen
Hello Prof, thanks for the great video tutorial.
I have a question: in the final layout results, S11 and S22, which represent return loss, is it okay if their values are not < -10 in this power amplifier design case?
@@canopuscapellavega Thank you for your support. Yes, there is always a trade-off between all parameters. As long as we can achieve the desired gain, PAE, and Psat, we do not need to worry about S11. We have applied a 50-ohm termination at the input, so these results were obtained under this condition. If you want to improve the return loss, you can adjust the matching network, but this may sacrifice other parameters.
HEY SIR I DIDNT THE FIRST COMPONENT AMP WHERE TO GET THE LICENCE PLEASE ?
It does not need a license, you can get the transistor model for ADS from Ampleon website and add it to the ADS as a library. In Design kit menu in the main page, there is an option that can be used for adding the transistor model.
Merci beaucoup Prof. Halim;
S'il vous plait, vous pouvez faire complete vidéos concernant design des circuits RF par ADS avec votre explications? depuis les bases au design avancée, ceci ils sera vraiment magenifique. On a besoin trés beaucoup comme cette contenu qui est rare...
Merci beaucoup pour supporter cette chaine TH-cam et pour vos recommendations. Je vais continuer à partager des vidéos tutoriel de conceptions RF, des bases aux circuits avancées.
thank you professor halim. Can I redesign with cascade 2 stage power amplifier with this transitor. What parameter value need resimulate, ex. Loadpull,.... Thank you!
Yes you can do it, as long as you do the matching to 50 ohm. But if you want to cascade, this transistor is going to be last stage. All parameters will be the same and you do not need to change them. But for your first stage, you need to do the load pull simulation again and extract the related parameters accordingly.