This is by far the most clear explanation in simple language about asynchronous design.. The language in Mano or CVS rao regarding this is too tough..Thanks a lot
Steps State Table - Assigning states in Truth Table Primitive flow table - stability wali table Reduced table - after grouping a,b&c Flow table - a,b,c as x1 and d,e,f as x2 Transition table - x1 as 0 and x2 as 1 SR latch - making S and R excitation table from transition table and SR truth table and then obtaining equation and making circuit.
I have a doubt regarding symbols: there are caps on insertion line |^ or an arrow with tail, in next state expressions for a gated D latch in the chapter 9: Analysis of Asynchronous circuits in "Fundamentals of Digital Logic with Verilog Design" by Stephen Brown and Zvonko Vranesic. How does the operator work?
It's very simple. At 28.43 I have shown a SR latch table in that y represents present state and the value inside the cells represents Y ( next state). By comparing it with SR Excitation table value we get the respective S and R values. For example in SR latch table consider the 100 cell( 2nd row 1st column) here the y = 1 and Y=1(value inside the cell) therefore the respective S value from SR excitation is x that can be marked at the position 100 of S map likewise for the same condition R value in SR excitation is 0 that can be marked at the position 100 of R map.
Hi mam i have doubt this question in tree format design procedure of asynchronous sequential circuit with two input x,y and output is z . behaviour of the circuit is given 1.intinally x=y=0 2.when x=1,y=0,z=1 3. when x=0,y=1,z=0
This is by far the most clear explanation in simple language about asynchronous design.. The language in Mano or CVS rao regarding this is too tough..Thanks a lot
Thanks a lot
Steps
State Table - Assigning states in Truth Table
Primitive flow table - stability wali table
Reduced table - after grouping a,b&c
Flow table - a,b,c as x1 and d,e,f as x2
Transition table - x1 as 0 and x2 as 1
SR latch - making S and R excitation table from transition table and SR truth table and then obtaining equation and making circuit.
Thank you so much sir, you helped a lot when I was lost !
Thanks a lot sir. Very nice explanation.
Spr explanation easy one on youtube
I have a doubt regarding symbols: there are caps on insertion line |^ or an arrow with tail, in next state expressions for a gated D latch in the chapter 9: Analysis of Asynchronous circuits in "Fundamentals of Digital Logic with Verilog Design" by Stephen Brown and Zvonko Vranesic. How does the operator work?
Thank you, my question is: what if your primiative flow table only had 5 rows how would you group the rows to form the reduced table?
Nice explaination
Sir last part samaj me nahi aaya :) 29:41 plz explain
It's very simple. At 28.43 I have shown a SR latch table in that y represents present state and the value inside the cells represents Y ( next state). By comparing it with SR Excitation table value we get the respective S and R values. For example in SR latch table consider the 100 cell( 2nd row 1st column) here the y = 1 and Y=1(value inside the cell) therefore the respective S value from SR excitation is x that can be marked at the position 100 of S map likewise for the same condition R value in SR excitation is 0 that can be marked at the position 100 of R map.
Crystal clear class thank you
Hi mam i have doubt this question in tree format design procedure of asynchronous sequential circuit with two input x,y and output is z . behaviour of the circuit is given 1.intinally x=y=0 2.when x=1,y=0,z=1 3. when x=0,y=1,z=0
Sir do we not need to draw the state Diagram in the second step before primitive state table
Sir ur explanation is good but apart from subject give some simple ideas to make it more easier
Regarding to priority
Where is the output map??
Present state (y) = Next state (Y)
Where Y is the output, therefore no need to find output map