Thank you for the video. Your series on serdes is very useful. Question: I am bit confused with the degenerative mode. so here we are trying to amplify the differential signal, but what slicing is done here. Sorry I may be missing something basic here. Thank you inadvance
Hi Venky, Nice to meet you. You're very welcome and thank you for the feedback. The regenerative mode is to amplify the differential signal to rail-to-rail logic level. The slicing senses the input tiny differential signal and outputs a rail-to-rail logic level, which is a nonlinear process of the slicer.
Thank you for the swift response Sir@@circuitimage In one of your training session on SerDes, Slicer is part of DFE and the information from slicer is feedback to summer. If the information from slicer is differential rail-to-rail, what information is being used by summer. Thank you again.
I am working on a project based on double tail comparators in cadence 90 nm, but the both outputs are same even if there is a difference in inputs ,Can someone help me with this?
@@rohitakki2504 The size depends on your speed & power, offset tradeoff: you might want to make the diff at least (W/L) > 8um/0.1um. The tail would be twice of it. The reset at the top would be half of it. Make sense? Thanks!
Great Video! I learnt many circuit insights/ideas just from this 10min video.
I will for sure check out your other videos.
Hi Abdolraouf,
Nice to meet you. Thank you so much for the kind words and I'm glad you enjoyed my videos.
Thanks,
CC
Very intutive & helpful. Great job 👍
Hi Jimmy, Nice to meet you. Glad it was helpful!
非常感謝學長一系列SerDes教學影片!!!
不客氣、很開心🥳我有機會幫到大家了解SerDes
Thank you for the video. Your series on serdes is very useful.
Question: I am bit confused with the degenerative mode. so here we are trying to amplify the differential signal, but what slicing is done here. Sorry I may be missing something basic here.
Thank you inadvance
Hi Venky,
Nice to meet you. You're very welcome and thank you for the feedback.
The regenerative mode is to amplify the differential signal to rail-to-rail logic level. The slicing senses the input tiny differential signal and outputs a rail-to-rail logic level, which is a nonlinear process of the slicer.
Thank you for the swift response Sir@@circuitimage
In one of your training session on SerDes, Slicer is part of DFE and the information from slicer is feedback to summer. If the information from slicer is differential rail-to-rail, what information is being used by summer. Thank you again.
@@CAPSTONEization Thanks for the good question. That's the ISI info was used by summer through the DFE calibration procedures. 😃
@@CAPSTONEization Hi Venky, the summer may just take the polarity from the slicer's differential rail-to-rail. Does that answer your questions?
I am working on a project based on double tail comparators in cadence 90 nm, but the both outputs are same even if there is a difference in inputs ,Can someone help me with this?
Hi Rohit, Nice to meet you. Yes, I can help you. 😊
@@circuitimage Hello Sir , I needed the transistor sizing for the transistors of the double tail comparator in 90 nm technology
@@rohitakki2504 The size depends on your speed & power, offset tradeoff: you might want to make the diff at least (W/L) > 8um/0.1um. The tail would be twice of it. The reset at the top would be half of it. Make sense? Thanks!