VERILOG HDL :Data Flow Modelling Examples

Learn to design Combinational circuits using data Flow modelling. Gate level modelling is compared with Data flow modelling with the help of few examples.
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[@ramchandraavusala8659]

Thank you very much Ma'am. Please continue the classes, don't stop. Your classes will be more useful to self learners.

[@yogeshkumar-zv1ix]

Thank you ma'am.... very well explained the difference between gate level modelling and data flow modelling now it is crystal clear that data flow modelling is more powerful and efficient for complex circuits :)

[@VeritasEtAequitas]

That's not dataflow. That is behavioral Verilog.

[@akshayarl843]

thank u mam..ur lectures are amazing that even a beginner can understand very well...pls continue the lectures which will be inturn helpful for self learners.

[@Jersey_Nani]

The best explanation 💯💯

[@mercymanjusha5163]

Wonderful lectures mam tq

[@TusharKumar-iu4nt]

Thankyou ma'am for this amazing video!!!

[@tanvipawar7822]

Thank you ma'am !!

[@nareshabhira8728]

Thanks fr the explain mam, Each is 5 mark ryt

[@VeritasEtAequitas]

Wrong. That is behavioral, not dataflow. There are 3 forms of Verilog. Don't confuse people by conflating 2 of them.

[@anjuagrawal4960]

Please double-check the facts before posting. This video discusses the Data flow modelling approach. Behavioral modelling is also discussed in the later videos. Please watch those too and clear your confusion.