- 64
- 268 465
AA
India
เข้าร่วมเมื่อ 28 ก.พ. 2012
ME(DTU),Ph.D.(DU)
Implementation of Full Adder on ElbertV2 FPGA Board: Watch and learn
The implementation has been successfully executed by Gauransh Bansal and Prerna Chauhan, who are currently in the process of learning Verilog HDL at DDUC, Delhi University. Furthermore, they have adeptly elucidated the steps involved in the process, showcasing their commendable understanding and execution of the task. Indeed, a job well done.
For Elbert V2 S3A FPGA Development Board details, click the link:
numato.com/product/elbert-v2-spartan-3a-fpga-development-board/
For Elbert V2 S3A FPGA Development Board details, click the link:
numato.com/product/elbert-v2-spartan-3a-fpga-development-board/
มุมมอง: 315
วีดีโอ
PLA
มุมมอง 261ปีที่แล้ว
Learn about Programmable logic arrays. Here few circuit diagrams are taken from internet and books.
PAL
มุมมอง 303ปีที่แล้ว
Learn about Programmable Array Logic Devices. Some circuit diagrams are taken from internet and books.
Design and Simulate Counters using VERILOG HDL
มุมมอง 791ปีที่แล้ว
Learn how to deign the different types of counters (up counter, down counter, up/down counter) using behavioral modelling. Also realize the importance of using hardware description language to design and simulate complex circuits efficiently.
Design Module and Test Bench for JK and T Flip Flops
มุมมอง 807ปีที่แล้ว
Learn to write the design modules for any given configuration of JK and T flip flops. Test benches are also explained in detail . You are set to simulate any flip flops using Behavioral modelling in VERILOG HDL.
Gauss Legendre Quadrature Method: Solve the definite integrals using Python.
มุมมอง 2.7Kปีที่แล้ว
Learn to solve the definite integrals using Quadrature Method and program this method using Python. The code has been demonstrated for one problem, but it works for any definite integral. The user only needs to change the function definition for the given problem.
Xilinx ISE: Design and simulate VERILOG HDL Code
มุมมอง 6Kปีที่แล้ว
Learn to simulate your digital designs using Xilinx ISE. This short video will save lots of time and will help you to start the simulation within minutes.
8085 Microprocessor Kit- Demonstration
มุมมอง 1.8Kปีที่แล้ว
Learn to load and execute the assembly language program on 8085 kit. How to check the register contents has also been demonstrated in the video by Divyanshi, student of B.Sc.(H) Physics III semester of DDUC,DU.
FPGA Programming : Demo of 4- bit Adder on FPGA board using VERILOG HDL
มุมมอง 1.1K2 ปีที่แล้ว
Aisha and Kamal, students of B.Sc. (H) Final year have demonstrated the working of 4- bit Adder. They programmed FPGA using hierarchical design methodology in VERILOG HDL. Xilinx Spartan board has been used for this purpose.
Behavioral Modelling in VERILOG HDL
มุมมอง 3.1K2 ปีที่แล้ว
In this video behavioral modeling is introduced. Two constructs- initial and always are explained with few examples. How clock signals can be generated for sequential circuits design is also explained in detail. The clock signals of any duty cycle can be generated using VERILOG HDL without any hardware.
FINITE DIFFERENCE METHOD: Solve second order Differential Equation using Scilab
มุมมอง 3.9K2 ปีที่แล้ว
Finite Difference Method to solve second order differential equation is explained in detail. Also it is implemented using Scilab. The general program is explained step wise in this video and it can be used for any second order differential equation.
Design D Flip Flop using Behavioral Modelling in VERILOG HDL
มุมมอง 7K2 ปีที่แล้ว
Learn to design D ff for asynchronous and synchronous Reset. Behavioral modelling has been used here to write the design module and stimulus. Clock signal in the stimulus is generated using always block. Behavioral modeling is easy to use for the simulation of clock-driven digital circuits.
Bisection method using SCILAB: Numerical Method to determine the roots of non-linear Equations
มุมมอง 2.9K3 ปีที่แล้ว
Bisection method: Numerical Method to determine the roots of non-linear equations is discussed. Its graphical interpretation and algorithm is explained. Finally, the method is implemented using SCILAB.
Gauss Legendre Quadrature Method using Scilab
มุมมอง 3.8K3 ปีที่แล้ว
Solve definite integrals using Gauss Legendre Quadrature Method in Scilab. Scilab program is explained along with an example.
Gauss Hermite Quadrature Method using Scilab: Example of Dirac Delta function
มุมมอง 5K3 ปีที่แล้ว
Gauss Hermite Quadrature Method using Scilab: Example of Dirac Delta function
Verilog HDL: 4-bit Adder using Data Flow Modelling
มุมมอง 3.5K3 ปีที่แล้ว
Verilog HDL: 4-bit Adder using Data Flow Modelling
Verilog HDL: 2 x 1 MUX using Data Flow Modelling
มุมมอง 4K3 ปีที่แล้ว
Verilog HDL: 2 x 1 MUX using Data Flow Modelling
Verilog HDL: Design and simulate 4-bit Adder using Hierarchical Design
มุมมอง 4.5K3 ปีที่แล้ว
Verilog HDL: Design and simulate 4-bit Adder using Hierarchical Design
Verilog HDL: Design Circuits Using Vectors
มุมมอง 2.5K3 ปีที่แล้ว
Verilog HDL: Design Circuits Using Vectors
Verilog HDL: Creating a Hierarchical Design for Full Adder
มุมมอง 3.1K3 ปีที่แล้ว
Verilog HDL: Creating a Hierarchical Design for Full Adder
VERILOG HDL :Data Flow Modelling Examples
มุมมอง 21K3 ปีที่แล้ว
VERILOG HDL :Data Flow Modelling Examples
GATE LEVEL MODELLING #3: Design and verify Full adder using Verilog HDL
มุมมอง 8K3 ปีที่แล้ว
GATE LEVEL MODELLING #3: Design and verify Full adder using Verilog HDL
GATE LEVEL MODELLING #2: Design and verify half subtractor using Verilog HDL
มุมมอง 4.7K3 ปีที่แล้ว
GATE LEVEL MODELLING #2: Design and verify half subtractor using Verilog HDL
Least Square fitting using Scilab: straight line fitting and polynomial fitting
มุมมอง 6K3 ปีที่แล้ว
Least Square fitting using Scilab: straight line fitting and polynomial fitting
GATE LEVEL MODELLING #1: Design and verify half adder using Verilog HDL
มุมมอง 11K3 ปีที่แล้ว
GATE LEVEL MODELLING #1: Design and verify half adder using Verilog HDL
Dot product,Cross Product, Angle between Vectors using Scilab
มุมมอง 3.6K3 ปีที่แล้ว
Dot product,Cross Product, Angle between Vectors using Scilab
Very helpful video mam thankyou ❤
Please add the default statement in the case statment. Else it will leads to latch up issue in the design
Very neat explanation
Thankyou
thankkkk uuuuuuuu 🤓🤓🤓
Thank you so much.chota packet bhara dhamaka
12 minute is very useful
bht bdia .. mam
Thank you so much ma'am
🙌👏👏👏👏
Thanks mam.
Ma'am thankyou so much ma'am im so grateful to you.. tqsm for buliding confidence inside me💗💗💗🙏🙏🙏
Very nice explain
Tq so much mamm😭app saviour ho
Mam you are like an angle from heaven for me ❤ thanks for guidence and knowledge❤😊
send full program in word
What does sigma represents here?
Wonderful video mam.
Best video in youtube regarding all the basics of matrix in Scilab
Nice explanation
Mam, how to solve LLGS equation using scilab
👌
Thanks mam. Thanks a lot
Do we do this code in xilinx Ise simulator? If we use xilinx, is that work or not ?
Mam , how to plot this solution in scilab?
I used the same code but it is showing error of inconsistent row/column in my scilab console.
Code should work.... check it again...if it doesn't plz share ur code here
@@anjuagrawal4960 i am also facing same issue
Thanks fr the explain mam, Each is 5 mark ryt
Thanks ma'am 😀 kuchh bhi nhi samjha 🐱
Very helpful mam u literally stop my headache 😂
Mam what is the need to change value of n Is more value of n means more accurate result?
Yes you are right, accuracy increases as more quadrature points are included.
I am not getting the line on execution but getting the points .....what to do maam?
great video
mam which software are you using for verilog coding
we are using xilinx ISE 14.7 but it also works on online simulator. How to simulate any verilog module using xilinx has also been made public. That video might help.
Thanku so much mam✨
Thank you ma'am ✨
Thank u ma'am ❤️
You are the best teacher and learning from you has been beneficial for me.
Great
Great job!
You are the best mam👏
acosd() can be used to obtain theta in degree
I think, in second and third summation equations n should be c.
when B is greater than A then, subtraction is not correct. how to fix that?
The best explanation 💯💯
Wonderful lectures mam tq
What about 3d?
great explanation mam
Thanks ma'am🥰
Wrong. That is behavioral, not dataflow. There are 3 forms of Verilog. Don't confuse people by conflating 2 of them.
Please double-check the facts before posting. This video discusses the Data flow modelling approach. Behavioral modelling is also discussed in the later videos. Please watch those too and clear your confusion.
Excelent video, helped a lot on a college project!!