CombCkt - 2 - Implementing Any Boolean Logic Function: Examples. Gate sizing

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  • เผยแพร่เมื่อ 22 ธ.ค. 2024

ความคิดเห็น • 4

  • @Prince_6299
    @Prince_6299 2 ปีที่แล้ว +3

    Thanks for such videos.

  • @ektasingh3508
    @ektasingh3508 ปีที่แล้ว +1

    but now width of nmos and pmos becomes same, so how will gonna follow delay symmetricity?

    • @ofek2852
      @ofek2852 5 หลายเดือนก่อน

      A good question.
      On the contrary, I would say you should use w=1 for the PMOS, because you have 2 in parallel what makes them act as doubled single one. hence, currently it is like you have a CMOS inverter of 4:1 ratio...
      He mentioned several times "worst case of PD/PU path". according to that, in case of the nmos PD, one should make it lesser resistive, unlike the pmos PU.
      still, it doesn't fit with intending to have a normalized delay as the CMOS inverter...
      in fact, there is a limitation with normalizing it. for example, try to normalize it in NAND3. (You can't because you don't have a pmos less then w=1...)

  • @monisraza181
    @monisraza181 ปีที่แล้ว +2

    The quality of teaching is non-pareil.