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Glad you enjoyed the video!

Thanks, that's good to know! I think the main difficulty with using 74HC/74HCT is that counters (like the '163 ones I used) can't meet the setup time requirement when clocked at 25+ MHz. I could almost certainly use slower parts for some of the other chips in the design. I actually tried out a 74LS153 as the pixel color selection mux, and it worked fine.

Thanks! I was definitely surprised that resolving the glitches was as simple as using 74ALS counters rather than 74ACT. For good measure I'm also going to replace the 74ACT157 mux with a 74ALS157 and the 74ACT273 chips in the row begin address register with 74ALS273. I think 74ALS is my new second-favorite logic family (after 74HCT, if course.)

Yeah, @@davehohacks, it was beautiful to see it working so well. By the way, I remember during your first attempt with the FPGA you concluded that you didn't know enough. I don't know whether you've come across him yet (and you may already be ahead of this), but John's Basement has a great series on FPGAs, using the ICE40's: th-cam.com/video/TJbI-NMJaUY/w-d-xo.html&pp=iAQB … I was going to go straight to FPGA, but you've inspired me to try the TTL route first. 👍

@@rogerramjet8395 I'm actually excited to pick up FPGAs again after doing this project with GALs and discrete logic. Thanks for the video recommendation, I think it will help a lot to absorb some proper background knowledge.

keep going!

@@joshc-dev Thanks! I'm working on a PCB, although routing is turning out to be...interesting.

If you search AliExpress for the term "UL1423", there's a listing from a vendor called "FreeBoom". I'm using the 26 AWG version. It's like 30 AWG wire wrap wire, but a little bit thicker.

No problem!

Noted. I'm planning to post alternate versions of Episode 03 and 04 without the background music (I hadn't realized that so many people felt strongly about this.)

@@davehohacks I figured it was probably best worth saying. I don't tend to like commenting negative things on videos, because boy it can hurt on the other end. But your content is so good otherwise I thought it was worth pointing out. I'm really enjoying this project!

Thanks, Troy! I've started working on the PCB. I think it's going to be pretty challenging to make everything fit. (BTW, I'd love to see a video about your Pi Pico TMS9918A replacement project.)

@davehohacks it's coming... I'm a big-time procrastinator. 🤣 The project itself is going great though. I finally have the single board version with the RP2040 onboard working.I have a few short, unedited, unlisted videos linked in the GitHub repo.

@@TroySchrapel I procrastinated on my display controller for 2 years, so I think you're making rapid progress. Looking forward to seeing it!

He was just doing some robustness testing 🙂

@@davehohacks :))

Thanks! Using a CPLD is an appealing idea. My main motivation for using an FPGA is the availability of an open-source toolchain for the Lattice ICE40 series. I think you're right that the current design wouldn't require a large device.

@@davehohacks the old Altera MAX7000 series is supported by older tools that are now free but not open-source, such as Quartus. however, they do offer a lot of design and simulation facilities that you may find useful.

@@TMITLT I'll keep that in mind!

That music is simply killing me thankfully it stops after 5 minutes

Maybe I'll post a combined video for episodes 3 and 4 without the background music.

Hey@@davehohacks … no worries for this one. (When I get some time, I'll mute it and read the subtitles …) But, I and clearly a few others would appreciate leaving it out next time. 👍🙏

@@rogerramjet8395 I think I will release alternate Episode 03 and 04 videos without the background music. Also, if you look at the "Episode03/Materials" and "Episode04/Materials" directories in the Github repo, there are scripts with the narration.

Good point.

Not hard to listen to, but not needed at all.

Yeah, I can't tell any difference between the MDR-V6s with the Aliexpress drivers and my MDR-7506s with the original Sony drivers.

One piece of advice that I should have heeded before working on an FPGA display controller: learn the simulation tool in whatever FPGA toolchain you're using. You'll see what I mean in subsequent videos 🙂. I'm actually working on a non-FPGA display controller right now, and it's going much better, but I'm planning to return to FPGAs soon, and I'm 100% certain that I will be simulating the design extensively.

Icarus Verilog is definitely on my radar! This current project has definitely convinced me that simulation is essential.

I did think about putting character and attribute data in separate RAM chips. I didn't realize that you could play tricks with A0 to make characters and attributes appear to be contiguous: that's a very clever idea. Allowing parallel loading of character and attributes would potentially double the throughput, which would be nice, although there's plenty of time to load characters and attributes sequentially, even with the relatively slow 70 ns RAM chips I'm using.

@@davehohacks a further idea relating to the need to start the RAM accesses in advance of the start of the visual area (and during the "previous" scan line) - I'd be tempted to drop an 8-bit shift register ('595 ?) as a configurable delay on the HSYNC line near the final output stage (such that it only affects the monitor's version of that signal). Alternatively some timing diagrams depict the 48 clocks of the horizontal back-porch being the start of the current line, and not the very end of the previous one, such that the line actually starts at the rising edge of HSYNC. This perhaps complicates the clock counters compared to starting the visual area at clock zero, but IMHO it sure beats having to think about doing stuff while the previous line is still going.

@@RayBellis Good ideas! I did consider starting scanlines with the back porch rather than the visible area, but eventually decided it was easier to just increment the vertical count early. (Although, now that I'm thinking about it, these are more or less equivalent ideas.) That ended up being a fairly easy change. I didn't think about delaying hsync with a shift register. Thinking about this right now, you could put all of the signals in a FIFO memory pretty easily and avoid the issue entirely.

I think I did look for 74AHCT parts and didn't see the ones I needed. It really is annoying that GALs don't guarantee more than 2.4V as the output high.

I'm definitely planning to return to FPGAs in the future, and I am confident that simulation will help tremendously.

It's very possible that parts of the design could be clocked at a lower frequency than the dot clock, although I haven't really considered doing that. If it allowed more of the hardware to work with 74HC/HCT parts rather than AC/ACT, that would be a significant advantage.

@@davehohacks I was mostly thinking about possibly less components, but that's just an intuition. That would need to be assessed...

@@RelayComputer That makes sense. Having to use fewer counter bits would be nice.

If you go way back on my channel to the early videos in the 8-bit computer series, there are some videos that go into more of the basics of address and data busses, bus control signals, etc. The nice thing about dual port static RAM is that it works exactly the same way as "normal" single-port static RAM, you just get two independent interfaces. Static RAM is very easy to interface. Also, definitely check out Ben Eater's videos on building a 6502 system if you haven't already. He does an amazing job of explaining things.

Wow, that's hard core! It wouldn't have occurred to me that auto-vectoring is possible on the 6809.

@@davehohacks Yah, you can determine when the CPU is fetching the IRQ vector by decoding BA, BS, and A1-A3. My ABUSSEL GAL uses that plus an additional signal from my interrupt controller to decide if the CPU or the interrupt controller gets to drive the address bus. (Eventually, ABUSSEL might also let a DMA controller drive the address bus, but that's pretty far off in the future.)

Thank you for pointing it out! Always nice to reduce the part count.

If you search for "UL1423" on AliExpress, there's a listing from a vendor "FreeBoom". I ordered the 26 AWG variant. I'm not sure if it's really 26 AWG, but it's definitely thicker than normal 30 AWG wire wrap wire. I've found it to be excellent for point-to-point wiring on protoboards.

@@davehohacks Thanks!

Thank you!

Glad you're enjoying it!

I guess when E is high the 6309 isn't accessing memory, so maybe your external device could sneak in then?

I think the software should be fairly straightforward. The only real complexity will be the bank switching, so the software routines will need to set the bank depending on which character or attribute they need to access.

Yes, this is just point-to-point soldering. I have done some wire-wrapping in the past. My only real objection is that wire wrap sockets are expensive.

I find point-to-point soldering to be therapeutic somehow.

Thanks! I think GALAsm only supports the Lattice GAL devices (16V8, 22V10, 20RA10) and compatible devices (like the ATF22V10.)

Right, the intensity bit gets added to all of the color component values, so it de-saturates the color. I believe that this is how the CGA text-mode colors worked, aside from brown being a special case. I might revisit the DAC at some point if I'm not satisfied with how the colors look (e.g., if there isn't enough contrast between the non-intense and intense colors.)

@@davehohacks In fact, this simple palette looks quite attractive. Especially if you adjust DAC network alittle, if necessary.

@@TomaTLAB We'll see how it looks once I (hopefully) get some characters displayed.

Wow, thank you!

🎉

Thank you!

Color in VGA is analog: each color component (red/green/blue) is indicated by an analog voltage between 0V and 0.7V. So, there isn't really any inherent limitation on the number of colors, but from a practical standpoint, there needs to be a binary number specifying the pixel color, so the number of bits you dedicate to each pixel will determine how many distinct colors can be displayed. Regarding resolution, there are standardized timings for various modes (the website tinyvga.com is a good reference.) I believe that some of the lower-resolution modes like 320x240 are generated by making each pixel wider (e.g., two clocks rather than 1), and then doubling each scan line.

That is a really good idea!