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GaAs, AlAs etc.

Planar type: yes, you need HR GaN for reducing leakage, bu not so for vertical devices, you need very good BSM (backside metallization) th-cam.com/video/8hS0hbBP9Kw/w-d-xo.html

@王不老說半导 So, the structure is Metal/SiN/AlGaN/GaN(drian and souce are ohm contact) from top to bottom, but for vertical GaN, it is Metal/AlGaN/GaN/Buffer..., isn't?

@@xyzmafour7207 GaN is more complex = GaN Channel + HR GaN...(high resistance)/Buffer/sub., Vertical GaN: see www.mdpi.com/2072-666X/14/10/1937

Will try, the info mentioned is a bit outdated. I need to include Notebooklm...

文中沒說電子的傳導率，只說的是熱傳導係數，有小口誤，牆高很薄，當然就可以穿透.

謝謝啦!

Thanks, glad that you like it! best wishes!

高手，感謝解惑，Robert Chau (my dotted boss in Intel) 研究此材料一輩子，選擇HfO2其實乃是試了許多，結果只有此材料比較好，期間甚至想放棄(imec 寫了一堆論文說絕不可能成功)，最後發現其defect bands not too bad and can be proteced by SiO2 IL.亦即reliability OK，every other oxides failed

Good inputs, can you be more specific, e.g., which page and topic?

hahaha, you are the one appreciate the weirdness in me. Thanks, i like it! Enjoy them, my friend, hardcore science can be fun as well.

good to know that you like my previous videos. Enjoy them!

Glad that you enjoy viewing them. I enjoy making them as well. My goal is to teach engineers in this field from all aspects of knowledge in a fun and entertaining manner. I live in Austin and am teaching remotely as a professor of NTHU_CoSR. I do not have an English nickname, but you can find me in my LinkedIn: www.linkedin.com/in/wei-e-wang-4911533/

glad you like them

glad that you like them:)=

基本上，網上是找不到的，我個人是想以後會製作相關視評的，但是常被其他看到的新東西分心，我建議你應該先了解統計分析，那才是真正的基本功， 現代工藝最後都必須以統計分析解釋，我做了一系列統計分析，我老王賣瓜，基本可以讓你很快上手的， th-cam.com/play/PLLqmCVy2iann-kmwLvFN3hzY-nRfUy95i.html

@@王不老說半导 多謝前輩。我一直有在反復看前輩製作的統計基礎視頻。

​@@tracygao169 good, did you actually run a statistical SW for practice? BTW, 個人以為，要了解全製程(如果想了解14nm/7nm/5nm這些製程的FEOL/BEOL流程?)，題目有些太大，很容易迷失， 建議你必須找到一個突破點，就是一個重要的與你有"切身興趣的主題"，你想法子去了解所有相關細節(包含如何DOE)，所有歷史及現在進展的"理由與結果"，一直專研到，你可以看到一論文，能夠知道其可行性，大概就厲害了，以此演再看此製程之其他延結部分，此招曰之"見縫插針，以點突破"，然後再擴面，方可知全貌， 建議多利用AI: Perplexity.ai，他推理不見得對，甚至很多有錯，但是挖掘references,一流也 簡單的說，你必須先是某主題的Content Expert，以此建立一種"信心"，再往其他主題，就容易多了!

@@王不老說半导 多謝前輩指點。學生之有用過JMP做一些簡單DOE，用來指引CVD機台的工藝開發。後來看了前輩的DOE視頻以後，加深了一些理論上的理解，也自學了一些統計知識，現在用DOE工具指引工藝開發更有感覺也更加有效率了。我本人也不在fab廠，所以對製程flow之類的知識了解的也比較少啦，就想多學習一下。感覺工藝開發這些東西後面應該都會被AI取代，所以可能需要拓寬自己的知識水平，提升工程能力，才能繼續在這個行業待下去？

@@tracygao169恭喜你走向正確的路! AI太恐怖，我們不是直接被AI打敗，而是被那些善用AI者打敗，所以你要成為善用AI者也!

glad you like them. I like them as well.

哈，ASML TD Director is my old friend. I know.

也許，所謂英雄造時勢，時勢也造英雄啊!

看來你對台積有些成見，若台積不靠一些生態圈幫忙，全靠自己及國外廠商的幫助，那麼就和三星，英特爾相同(英特爾得到國外廠商的幫助更多)，那麼台積也太厲害了一些。

The links are in the presentation (bottom of each page). Let me know if you want a specific one.

Thanks!

I consider myself a process guy, not a design guy. I approach each topic from process perspective with limited introduction of design layout, except those which can impact processes tremendously. HBM uses regular DRAM except they have to stack them together, say 4,8, 12, etc., by a process called MR. MUF (liquid wax with higher thermal conductivity k) of SK hynix or NCF (better control of a plastic film but lower k) of Samsung, or in the future HBI (perfect world, using tool from EVG or Besi). In addition, the bottom die is critical. TSMC will use their 12nm logic for this. Samsung is far behind in this. DRAM is no big deal, these memory maker can make them with high yield. However, stacking them together using W2W is a yield killer. e.g., the new yield is 80% if the two wafer bonded together using W2W with each having 90% yield. What happens if you have 12 wafers to be bonded together. The total yield could drop to 25%. Stacking is costly. Even you solve the DRAM stacking issues, then the challenge is to put them together without warping or particles since you want 100% yield. The power rating for the crazy AI chips are a round a few kW, they can be hot like crazy. The thermal stress induced warpage is a nightmare...

@@王不老說半导 Thanks a lot, Dr. Wang! Sorry for the DRAM design questions! Exactly due to the large amount of TSV embedded, thermal/power control and more issues for DRAM, some special measures have to be taken to make the DRAM appropriate for HBM applications. I am wondering what are those have been adopted and what are those to be coming. It is very interesting, I guess. Again, appreciate your prompt reply.

@@qz9514 DRAM is super sensitive to temperature. It starts to act weird above 85C. It's dead above 90C. They have to refresh regularly (every 64ms). This means bottom die has to do something just to keep them alive. This adds additional heat burden to HBM. Guess you're right DRAM guys need to do something about this by making some special DRAMs as you mentioned earlier. However, this usually mean downgrading the best best DRAM currently we have. Who is going to come out with this new DRAM in time is a question mark, HK hynix or Samsung? Some of my DFM ideas are discussed here for TSV: th-cam.com/video/C5juSIAPgZU/w-d-xo.html&lc=Ugy6YjFBqgwuf8ipG4R4AaABAg The newest DRAM are 3D DRAMs, which could mean more DRAM capability with less footprint. How that impacts HBM4 or higher is anybody's guess.

@@王不老說半导 Thanks a lot, Dr. Wang for the continuing sharing. One thing that I know is that s decreased number of WLs per mat, which makes fewer DRAM cells attached to a BL and reduces BL capacitance. The reduced BL capacitance and the amount of voltage developed by the charge sharing between a BL and a cell increases as BL capacitance decreases, thus reducing the sensing time. This suggests the DRAM for HBM could use smaller MAT size for higher reading speed. The other thing is the real estate management around TSV for HBM interconnection. There shall be a certain exclusion zone around tsmc for DRAM cells due to the possible high strain generated from Cu filled TSV. Here are couple things that I can think about. There shall be more to differentiate the regular DRAM and DRAM for HBM. Thanks.

@@qz9514 Thanks for sharing your keen insights especially about TSV. TSV does introduce extra stress issues. But the stress has little impact to DRAM performance since they already leak like crazy. However, I believe the issue has been captured and solved since TSMC has used them on the current AI chiplets using TSV and HBI, except that they need to include many more DRAM stacks. The learning are to be ported for sure.

I could not find them. Sorry!

多蝦啦! 可以到清大找...或 th-cam.com/video/YNEHlqkj23Y/w-d-xo.html

Looks like fancy games people play to get publication. Industry does not like them due to cost and no guarantee that the benefit are still there after all the steps are done.. GaN Dit are so hard to passivate, as explained in the video. I simply won't trust these fancy SC (they tried to get themselves into Si-CMOS process flow and failed)

in mVt (HKMG steps)

也替你高興!

加鋁是論槍打鳥的結果，我和發明人之二，Suma Datta and Uday Shah 聊過此事，Intel CR 此發明做的實在不錯，他們本來也沒有想到鋁有效，鋁的熔點太低(660C)，任何原子在2/3熔點時就會亂動的，對後來製程將有巨大限制的， 至於印刷術是中國發明的嗎? 此討論有意思，沒有人云亦云，可以參考， th-cam.com/video/UTB9kOIi5MM/w-d-xo.html

IBM文化本來就不適合HVM，良率沒有高過，然而其原創力與專利，世界第一，確有其厲害的地方， LaO不是成本問題，而是量產時會有其他問題，LaO沒事會自己膨脹的，很麻煩，還有其他..

感謝建議，highl 1st or last is indeed a good story...Vt control is one of the key parameters to be controlled. However, my message is about the thought processes (the role of the demon), not too much about the exact technical content.

Thanks!

Glad you like them!

AI目前是如此，以後很難說!最近的論文宣稱Cereberas芯片運算能力，已經在微觀原子數大大超越以前能力

exactly!

一針見血

妙喻!

100% agreed: 學物理化學 必須要有想像力 是一個必須的技能, 電子 穿梭與chemical potential are linked. chemical potential 的定義，非常有意思的! en.wikipedia.org/wiki/Chemical_potential

Good eyes! left side is correct. P should have opposite sign... Right side figure is wrong.

了解! 謝謝回覆😊

Thanks!

SiGe非常麻煩的，passivation Dit 很難，其他process 還有一堆問題(Ge diffusion, N/P boundaries, etc.)，所以Samsung 與 Intel 研究很久，但根本沒有真正用過，台積若真正能做，確實世界第一，沒話說，以下是個人臆測，純屬參考用: 但台積沒有公開說3nm用SiGe，5nm/3nm 其實fin變化不太大，5nm能用，3nm應該都繼續用，如果台積3nm用SiGe，應該也會宣傳，大家必大大喊讚，但台積沒說，這就令人有些疑惑，因為一個新的，厲害的，大家都做不出來只有你會的，會形成一個new baseline, 若只用一代，那就怪怪的

@@王不老說半导台积一向不喜欢透漏细节，我是看到techinsights报告，TEM比IEDM paper透漏了更多细节。而且N3比N5 Ge concentration略低，可能是量产过程中碰到问题。N3采用了一种非常巧妙的方法来解决NP boundary问题，side effect就是SRAM面积几乎没有微缩。

@@王不老說半导 Finflex PPA足夠應該就不需要高風險的技術了XD

@@王不老說半导 想問老師 SiGe 的concern 主要會落在 long term reliability (BTI, TDDB..) 還是會落在Performance上(Dit SS Leak...)

SiGe 其实有利於reliability bc VBO better. IBM 有paper.. 他的主要问题在介面缺陷及SD必须上调Ge, 以保持strain, 但Ge 会熔点下降.. boron diffusion 也是问题.因为junction steepness 会出问题

謝謝批評，我做視評，主要是自我學習，也是一種摸索的過程，必有自己一些不成熟的特色，所以有些自我感覺良好的缺點，但也是沒辦法，若想深入探討某課題，可以提出一個真正問題，例如以下讀者與我對CNL的細節討論: th-cam.com/video/n4R4rt7dLFg/w-d-xo.htmlsi=kuOkpE2jWC98i22n 或者到清華大學選我的課，也無任任歡迎的

Glad that you find it useful!..

very good questions indeed. I will try answer your questions the best I can. Below are just some quickies for now. Will get back to you for more details later.. 4.: No band gap is b/c no ions. Eg concept is from the existence of ions where electrons cannot penetrate. This is shown in detail by my video below: th-cam.com/video/ClRbvmhFxZA/w-d-xo.html 1&5: As I mentioned in the lecturer, CNL is a materials surface intrinsic property. It has no connection with the Fermi level. Fermi is not an intrinsic property since it is altered by doping. The detail calculation of CNL is very complex. Please check out the ref. mentioned in the talk. The polarity of charge at surface, however, depends upon the position of EF w.r.t. CNL. It's negative when EF is above CNL charges and positive when below. CNL and EF forms a relationship from which the resulting band bending (QSC), Qit and Qm are balanced in a way to preserve neutrality. A perfect alignment between CNL and EF is an ideal case in which no band bending.. 2. No dangling bonds for 2D, but metal can react with 2D (hydridation) to form MIGS. 2D crystal in not perfect as well (subsurface impurity still can cause havoc.). BTW, you don't need much to pin. The Dit of Si-CMOS is in the range of E10/cm2. The surface atomic density of any material is around E14-E15. Any impurity on the surface, not observed by any physical apparatus (their sensitivity is only 0.1% at best, i.e., E13) , can still pin the Fermi level (electrical signal is a lot sensitive). 3. I would think so.

老師好 感謝老師的回覆與分享了MIGS這部影片的連結(th-cam.com/video/ClRbvmhFxZA/w-d-xo.html) 我也順道把在另一部影片談論了surface states看完了(th-cam.com/video/cxJPkBx-Jhw/w-d-xo.html) 還有後續幾個影片也一併看了 前陣子真的尋找好多相關文獻，在試圖了解這個Fermi level pinning的這個問題 根據老師的影片我終於理解到的是就是surface states與 metal induced gap states是可以類比的東西，一個是要描述在半導體表面因邊界條件改變而形成的能態，另一個則是因為半導體表面接了金屬而變成介面態，而他們都共用一個圖像就是會形成了一堆連續能量的states在原始半導體的帶隙中，這些states的數量會成指數衰減到到CNL的位置 而表面缺陷或雜質則會在材料中創造一個在特定能量位置的states 先前我也一直覺得沒辦法很好的把這些states的區別給搞清楚，但現在有比較理解了 但我還是有好多問題在我仔細思考過一樣存在 1. 是關於CNL的問題 在上一個問答的內容裡面，我想我忽略的這個CNL與Fermi level之間的關係是討論在電中性條件之前還是之後了 想跟老師確認的事情是在電中性平衡之後，CNL與Fermi level 應該會在同一個位置對嗎? 否則能帶應該要繼續彎曲直到達成電中性平衡對嗎? 2. 關於這些連續能量的states 在老師的影片與一些發表的文章都可以看到這些states的數量是指數形式的衰減到CNL的位置 想知道為甚麼這些states的數量會是以這個形式指數衰減到CNL的位置？ 而CNL為甚麼會是states數量最少的能量位置？ 3. 關於這些連續能量states的存在區域 在老師的影片中描述了這些states的存在是以指數形式從介面/表面衰減到半導體內部 如果是這樣的話，假如觀察半導體從內部到表面的能隙大小，是否也是會呈現一個指數變化，從內部有能隙，能隙大小指數衰減到0而進入表面 我只是在想這個半導體的內部與表面應該會有個過渡區域，那能隙的大小好像就會像是被這些states給填上而縮小的感覺 不知道這樣的觀念是不是有誤 4. 關於使用絕緣體來減少MIGS 依照絕緣體的圖像，絕緣體可以是能隙比較大的半導體 金屬與絕緣體接觸不會產生MIGS而造成Pinning嗎？ --------------------------------------------------- 近年對一些單層的過度金屬二硫族化物感興趣(TMD) 有看到一些文章講二維半導體生長在金屬上，如單層的MoS2生長在Au(111)，即便表面沒有看到任何缺陷，其實從能譜上也無法辨識能隙的準確位置 這些能譜除了特定能量位置有峰值以外，其他能量位置都還是有DOS可以量測到 在稍微了解了MIGS，之後，我頓時感受到很神奇，儘管沒有任何晶體缺陷產生被觀察到，但這些交互作用確實創造了states，並填滿了整個能隙 相比MoS2生長在HOPG這種半金屬基板上，能隙就顯得乾淨的多 為了去了解MIGS，我深感半導體與金屬的接觸真的很複雜，儘管很多文章發表，好像仍然有很多規則還沒有被確立 好比說CNL應該存在的位置，從老師的影片中就有看到有的人說跟H在晶體內的能量位置有關，有的說在dangling bond的能量位置有關 有的又會說跟缺陷的states在哪裡有關 但我會感覺CNL存在的位置應該是最容易產生缺陷的那個能量位置，就會是CNL的位置(雖然我也不知道對不對，也沒有證據，只是瞎猜) 但這個想法是源自於MIGS在TMD材料生長在金屬上的文章，由於大部分金屬與這些TMD都是pinning在N-type 的區域(即便材料上沒有觀察到任何缺陷) 而這些TMD材料，最容易生成的缺陷大多數都是硫、硒空缺，這些空缺都是被預期會在CBM下方產生一個in-gap states 恰好與pinning在N-type 區域好像有連結性 總之還是相當感謝老師辛苦製作影片，我真的收穫良多 也盼望能與老師持續有交流 Bests

@@Scola_Hao have fun!

@@Scola_Hao contact me thru my gmail in my LinkedIn . We can the connect thru LINE for easier discussion www.linkedin.com/in/wei-e-wang-4911533/ You need to keep in mind (as I mentioned earlier). All physical measurements are quite limited in understanding defects. This is because (a) your STS measurement area is so small and (b) the sensitivity of STS is inadequate to see the electrical response (down to E12/cm2 or below). This is just statistics. The sampling area is too small. You can use a TEM to see no defect and yet there could be tons of defect in reality, e..g, to see defects density of E8/cm2 need to sample 1umx1um. TEM area is a few nm or a bit more. There is no way for them to see defect density < E8/cm2. BTW, the surface has no band gap is b/c electron can go anyway since they do not see ions blocking their paths... 2D materials is a bit more complex. Please check the most recent papers on this subject (VIGS?) pubs.aip.org/aip/jap/article/135/10/100901/3269952/Native-point-defects-in-2D-transition-metal pubs.aip.org/aip/sci/article/2020/30/301104/364696/Extending-the-metal-induced-gap-state-model-to

Thanks, feel free to check my contact info in my linkedin www.linkedin.com/in/wei-e-wang-4911533/