Construction & Working of Enhancement-Type MOSFET (Part 2)
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- เผยแพร่เมื่อ 15 ธ.ค. 2016
- Analog Electronics: Construction & Working of Enhancement-Type MOSFET (Part 2)
Topics Discussed:
1. Threshold voltage.
2. Complete MOSFET circuit.
3. Working of Enhancement-type MOSFET.
4. Pinch-off in Enhancement-type MOSFET.
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No seriously man I saw ur vid in 1.5x both part 1 and 2 and understood what my teacher took 1 hour to explain and me not understanding a single word. Thanks man keep up the good work!!!!!
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In case 2, As Vds is increased, the reverse biasing also increases( Drain terminal connected to n-type well and also given positive voltage). As reversing biasing increases, the depletion region increases, and because the depletion region increases, there is lesser and lesser flow of charges.
Thank you for this
Thank you
Thanks a lot! I was having problem with this case.
Thanks
Does his explanation imply that Vds>Vgs?
The most exciting part of the video is that the Kirchhoff laws are marked in the subtitles, which is the key to understanding the second half of the video.---from China
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For case 2...before Vds was increased there was a forward bias due to Vgs .by increasing Vds you reduce the effect of the forward bias since the drain terminal is connected to the +ve terminal hence depletion layer increases
Thanks for this easy explanation.
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When drain becomes more positive the potential difference near the gate source region becomes less positive . So the attraction force becomes less .But toward source terminal it's grounded so gate source voltage difference is high enough to attract the minority carries from bulk
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Please talk more on pinchoff region and body effect.
Excellent
Hi.. thanks for the excellent video. Can you tell me which book you have followed in making this video? I need some more explanation about a few things.
Thanks
Case 3: Think of it as a line segment with 3 points: S------G------D (similar to the MOSFET)
If we need S+G to overcome the VT threshold, then we could say, we need S+G to get to D. With this understood, then we could say, S+G = G+D are of equal length. Now, D+S is a total length of the line segment and remember, the line segment is broken in 2 equal parts: S-----G & G-----D. If you understood my 2nd sentence, then we could also say S-----G---VT---D because we need the length of S+G to get over the threshold (VT) to D. If the line segment is 2 equal parts, then: S---VT---G & G---VT---D... so if we took away S+G, then we are left with G--VT--D, thus VGD = VT. I hope this brought some clarity.
Thanks!
sir ...plz upload lecture on classes of amplifiers
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For people having doubts in case 2, think of it as a reverse biasing a P-N junction.
when vgd becomes more positve how can drain become less positive(case2)
Life saviour
Case 2 not clear 😫😫
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sir I m not understanding case 2 and3
For case 2 think of a normal diode...
Now apply +I've terminal of battery on n side and -ive on p side as in case 2 in drain.... Now think if it's reverse bias or forward I.e reverse biased so deplition layer increase....
thank you very much. I have seen it 5 times but got clarity after your explanation
What do you mean by uncovering of ions? Which ions? Which electrons? Those what are bound with Intrinsic semiconductor (Si or Ge)? Or Doping material (B, Al)???
Sir in case 3 when Vds=Vgd-Vt
Then Vgd=Vt
Then why the current is not equal to zero as width of channel near drain is zero
Sir in case 2 when u say drain is becoming more positive the width of the channel reduce and depletion will increase why.?.... when it is positive then width will increase and depletion will also increase because of increase in reverse bias potential ..... sir plzz clear this out
Width of channel and depletion layer cannot increase at the same time
Sir I did not get the CASE 2 and CASE 3. Sir please do make a new video to explain in detailed way...I saw the video 3-4 times but still did not understand what are you trying explain in those two cases..Plzzz help us in those two.....
sir please give an lecture on transistor as an oscillator.
Sir you have told that we try have only one biasing source. But you use two source at Vgs and Vds
Whem Vds = 0 there will be no Id right? Since both the source and drain are at same potential?
Sir a question arise in mind that if G has more positive then P type material having minority's charge carrier will flow toward Sio2 then due to less content of e why are not recombination between hole and e then how could e generated on other side of G
What happens when you have too many biasing voltages plz explain about that point
Good
how can current flow in case 1 when we make vds =0 there should be potential difference across the terminals for flow of current may be both channel widths would be equal but there wont be any conduction
sir please upload Amplifier tutorial...
Sir we connect source and body terminals because we do not want too many biasing sources.So why do what is the special reason of connecting source to body and not drain to body?Can we connect drain terminal instead of source terminal to the body.
sir in this video i think the biasing will be of opposite polarity....
pls confirm this.....is it right?
Shouldn't the Id current flow from Drain to source?
At 14.58
When you are telling about the thing that when drain becomes more positive, less positive charge and hence less electron interaction.
But since drain is becoming more positive,shoukd the force of attraction increase and so channel width increase and depletion region reduce?
Drain is becoming more positive w.r.t. gate, however, gate to source voltage is constant. Hence channel width between gate to source will remain same. However, more positive drain implies more reverse bias between drain and gate and hence channel width will reduce.
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@@abhikumar6335 can u pls explain the third conditon or case
Hi sir
In case 2, channel width is getting reduced. What about current flow in that condition whether the current increase or reduce? Because in drain char. when we are increasing vds current also increase. How can current flow increase when channel width is reduced. Pls clear this sir.
I didn't get Case 1. Why would the voltage between D and S equal zero? That actually means that there's no current flowing from Source to Drain. It's kind of paradox to me. On one side the channel is opened (which means that the current is moving from Source to Drain) and on the other side Uds=0 (no current flows from Source to Drain).
I have a doubt. In case 1 you said that we will keep Vds as 0. That means drain and source are short circuited.
If drain and source are short circuited, why should be there any current flow through the channel??
By saying keeping Vds =0, he means that there is no Vds at all.
I don't think there will be any current flow in that case. We're not discussing current vs Vds, just just depletion layer and channel width.
"SIGNIFICANT CURRENT FLOW" what does this significant mean?? nA or mA or uA??
Vgd influences if the depletion layer is uniform or not.
How can the depletion layer be equal when one of them is forward biased and the other one is reverse?
Sir i have one doubt mosfet is symentrical device but y we are cal it as source and drain
sir i didn't got case-2. If drain is becoming more positive than why did drain region gets less positive voltage than source region?. please answer it sir
I also can't understand
i also can't understand case 2...why ain't u answering...?
I think it is because when Drain terminal gets more positive, electrons from the Drain's N-well gets attracted and Holes from the N-well's vicinity gets repelled which increases the depletion layer which means less majority carrier consequently leading to less current conduction. If I'm not mistaken with this regard, less current means less voltage. If I'm wrong I'm more than happy to be corrected.
Rupanshu Kapoor , Suppose that Vgs is fixed at 8 V , and if u increase Vds from 2 V to 5V, Vgd will decrease from 6V to 3 V, this reduction in the gate to drain voltage will, in turn, reduce the attractive forces for electrons and the width of the so-called enhanced channel will also reduce due to fewer electrons .
see i think if drain voltage is more positive then it will act as reverse bias here in which depletion layer width increased since vd is given to n and p is given ground .this will make u understand why depletion region increased
In case 01 at 10:04 after applying kvl I am getting Vg + Vgs - Vds - Vd = 0 . Sir can you please check it why ?
Case 2 and 3
I like u, sir.
why we are finding conditions for Vgd ?? i didnt get it??
Does his explanation imply that Vds>Vgs in case 2??
Why the channel width is decreased only near drain for CASE 3
if drain is becoming more positive and we also giving positive potential to th gate..then ..both ..positive voltages.will combine and will make ..drain side more positive ..so the channel ..must be wider at the drain end..buy in video ..you have told just opposite ..that channel is narrow at ..drain end ..why ..is my explanation is wrong . ..pls explain me..!
dekh bhai
let's assume that initially Vg is 4 volts and Vd is 0V
but now vgd is decreasing in case 2
it can be possible when vd becomes more positive.
as vd increases it attracts electons toward sio2 layer,making channel narrow.
In the three case why you have not consider case of V(DS)
Beacuse electrons wants to flow from source to drain ...so we considered the case vDS>o...if we apply vDS
how drain current would change with increase in Vds
why does V(ds) even matter, shouldn't the channel width be totally dependent on V(gs)??
can anyone explain me 10:4 Vg-Vgs+vds=VD i want to know Vg-Vgs+vds+vd = 0 KVL says total voltage sum = 0
why does channel become narrow at drain ? and not at source.
Small doubt why don't you use white background if you can use it, then all the writings are clearly visible
Can u explain case 2 nd 3 again . It's very confusing nd it's not clear. Case 1 is very clear.
Sir please cover remaining lectures on amplifiers as soon as possible. Thank you sir
2nd case explanation
when Vgd goes down it means increasing of the drain voltage and reduction of gate voltage......but assume the gate and drain as the terminal plates of a single capacitor having positive charge accumulation at gate and negative charge accumulation at drain....what happens when Vgd goes down in this capacitor....some of the negative charges at drain will flow to the gate causing reduced negative charge accumulation at drain....as a result channel width reduces
Nice explanation but please clear the board from time to time while explaining it is easy to understand. When writing case-2 and case-3 the diagram was not visible.
Case 2
vgs ka symbol dono jagah same??
case 2 and case 3 is not clear to me... help me out