Thank you for the explanation. May I ask a question sir? Do we have access to the inner bulk (inside well) of Dmos transistors and connect it to a desired voltage? Im working with a 0.18 micron bcd process and in the symbol of all dmosfets (pldmos and nldmos) there is just a forth pin named as p_sub. I wonder if it is the common p_substrate contact or something else?
@@jayateerthar5224 yes it is isolated but seemingly there is no explicit pin connecting to it. All I have access to in the symbol are gate, source and drain pins and a fourth pin named p_sub. Im a bit confused but I guess we only have access to the shared p_substrate which needs to be grounded anyway.
Max RF power and frequency depends on number of factors....assuming 12V NLDMOS, Ft would be around 30GHz and Fmax would be double of that.. and currents can be as 10A to 15A depending on the foundry... But now a days GaN is picking up in this area for extremely low RoN...so, size goes low enabling even higher frequency of operation at high powers...
Very clear, thank you. When you say we need an isolated nmos in that dc-dc example, is that because of the large body-effect it would have otherwise? Or maybe because of possible maximum ratings between source and body?
For the top PowerFET yes, body-effect would be large as the voltages will be high and it will defeat the primary purpose of using NMOS device to save area and reduce parasitic(lesser switching cv2f loss also ; for a given conduction loss). Max rating for source and body will be much higher....for a 12V LDMOS, VGS rating would be 5V, VGD, and VDS would be 12V but VSB or VDB would be generally higher...I have seen 30V kind of figure...but better to double check with process node used from a particular foundry..
Thank you so much!! It's very clear and easy to understand
Thanks for the feedback
Good explanation on DMOS. Thank you!
Great explanation! Thank you!
Thanks
DE MoS For HV application
Double diffusion MoS (n~ n+
Lateral Dmos ( n+ is placed in nwell )
Both are asymmetrical
Many thanks!
You're welcome!
Thank you for the explanation. May I ask a question sir? Do we have access to the inner bulk (inside well) of Dmos transistors and connect it to a desired voltage? Im working with a 0.18 micron bcd process and in the symbol of all dmosfets (pldmos and nldmos) there is just a forth pin named as p_sub. I wonder if it is the common p_substrate contact or something else?
Yes.. generally it's available..
Sometimes even the high side switch of the DC-DC will be bulk isolated nmos transistor...
@@jayateerthar5224 yes it is isolated but seemingly there is no explicit pin connecting to it. All I have access to in the symbol are gate, source and drain pins and a fourth pin named p_sub. Im a bit confused but I guess we only have access to the shared p_substrate which needs to be grounded anyway.
Nice explanation and plots. What is the current frontier in LDMOS in terms of max Rf power and max operating frequency?
Max RF power and frequency depends on number of factors....assuming 12V NLDMOS, Ft would be around 30GHz and Fmax would be double of that.. and currents can be as 10A to 15A depending on the foundry... But now a days GaN is picking up in this area for extremely low RoN...so, size goes low enabling even higher frequency of operation at high powers...
Thanks, that is helpful. RoN = ?
RoN= On Resistance, generally expressed as RsP (resistance per unit area; generally will be around 15milli ohm/mm2)
COOL
thank you sir
Very clear, thank you. When you say we need an isolated nmos in that dc-dc example, is that because of the large body-effect it would have otherwise? Or maybe because of possible maximum ratings between source and body?
For the top PowerFET yes, body-effect would be large as the voltages will be high and it will defeat the primary purpose of using NMOS device to save area and reduce parasitic(lesser switching cv2f loss also ; for a given conduction loss). Max rating for source and body will be much higher....for a 12V LDMOS, VGS rating would be 5V, VGD, and VDS would be 12V but VSB or VDB would be generally higher...I have seen 30V kind of figure...but better to double check with process node used from a particular foundry..
@@analoglayoutdesign2342 Great, thanks.
Please anyone explain in mosfet we are using only p substrate and in Ldmos we are using psubstrate and pwell why ..
We will have drift region... that's why
Sir please tell why in Ldmos pwell and pbody is differently doped
Do you mean p- well vs p+ contact? To form a contact you need high doping levels. For high break down voltages you need low dopings.
Anyone can help me to give a connection diagram of ldmos for 1030 MHz and 1090 MHz.