Digital Design & Computer Architecture - Lecture 5: Combinational Logic II (ETH Zürich, Spring 2020)

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  • เผยแพร่เมื่อ 3 ม.ค. 2025

ความคิดเห็น • 7

  • @aaardvaaark
    @aaardvaaark 4 ปีที่แล้ว +9

    These are awesome and thoroughly enjoyable lectures, they really fill in the gaps between the transistors and the cpu architecture ie. the PC, ALU, registers etc.

  • @shah.kairav
    @shah.kairav 4 ปีที่แล้ว +8

    Recap ends at 27:00

  • @shah.kairav
    @shah.kairav 4 ปีที่แล้ว +1

    At 1:06:50, I feel that the output is not correctly mentioned because s0 refers to the second digit of the input while s1 refers to the first digit. Hence, the truth table should be:
    1. 00 -> D0
    2. 01 -> D1
    3. 10 -> D2
    4. 11 -> D3

  • @Tapeesh.M
    @Tapeesh.M 3 ปีที่แล้ว +1

    44:06
    F= A+BC
    Can some explain how it resulted from second last step?

    • @Alluring_Penguin
      @Alluring_Penguin ปีที่แล้ว

      You can group A'BC to A'(BC). With this knowledge A + A'BC = (A+A').(A+BC) and (A+A') = 1 so solution of the equation is F=A+BC

  • @veeramani-jo7kw
    @veeramani-jo7kw 2 ปีที่แล้ว

    Can any one explain why tri state buffer is preferred in CPU/Memory data, as both control signals are high it will be in treble. why don't we go with multiplexer here?