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At 8:16 - 8:17 I think there should be AND gate instead of NAND gate because In the video of preset and clear you taught that clear works when clear = 0. Since it is already active low, a high signal should be applied to clear. Otherwise what is point of using two continuous NOT gates (1 inside NAND and 1 in active low bubble) before applying signal to flipflop cell.
I think for active low clear (if clear=0 then output will be zero) so if we give nand gate it makes all output to '1'..so I think AND gate is correct for this circuit
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sir i have a doubt! what happens when clear is 1? like in the before cases when the output Q3Q2Q1= 010 or 101? and will it stop after 110? why wont it go till 111?
If any one input of nand gate is 0 then the output is 1 so this nand gate will give output as 0 only and only if the input to nand is 110 so when this condition come then nand will give 0 as output and this 0 will goes to clear and reset the counter
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All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us. Your positive comments motivates me and person like me get boosted by my students feedback. Thanks and welcome 🙏
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Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.
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@@vimala8508 state will go to 1 1 0 but as he goes to 110 the clear will do his job and make the output 0 0 0 if we make it for 1 0 1 then it will not count 5 instead of 5 it will give 0 0 0 that's why we take 1 1 0
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Thank you sir, lots of love from IIT Guwahati 👏🥰
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Great video sir ,LOVE from Bangladesh
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1:05 there is no moment in hand so I thought my video got stuck but actually what happened 😂
Thankyou sir❤ NIT Jalandhar
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Thank you professor
Love and happiness of students is my ultimate goal, God bless you 🙏, keep learning and keep progressing.
At 8:16 - 8:17 I think there should be AND gate instead of NAND gate because In the video of preset and clear you taught that clear works when clear = 0. Since it is already active low, a high signal should be applied to clear. Otherwise what is point of using two continuous NOT gates (1 inside NAND and 1 in active low bubble) before applying signal to flipflop cell.
Bubble means active low
I think for active low clear (if clear=0 then output will be zero) so if we give nand gate it makes all output to '1'..so I think AND gate is correct for this circuit
The explanation is just amazing. It is maintaining my curiosity that's the best part.
Thankyou Professor :)
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Well teaching sir
Your positive comments motivates me, Thanks and welcome 🙏
thanks ,understood
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Sir so we can make all these counters by the use of any flip flop?? Only thing is that its connections change...
Yes
Nice teaching skill 😄
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0:33 0:37 0:37 0:39 0:39 0:43 0:43 0:43
sir i have a doubt! what happens when clear is 1? like in the before cases when the output Q3Q2Q1= 010 or 101? and will it stop after 110? why wont it go till 111?
When you use active high clear.. 101 should be given as inputs to And gate
After 101,it goes to 000..because all the flipflops are cleared or reset
If any one input of nand gate is 0 then the output is 1 so this nand gate will give output as 0 only and only if the input to nand is 110 so when this condition come then nand will give 0 as output and this 0 will goes to clear and reset the counter
THANK YOU SIR
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0:05 0:11 0:13
Thank you Sir from Bangladesh.
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sir please make problems on digital electronics for gate
See the playlist, you can,solve any questions on GATE as well.
sir is that any reason to use t flip-flop for design asynchronous counter. which other flip-flop can be use for design asynchronous counters.
It gives advantage of toggle and counter needs that only
@@EngineeringFunda can I use any counter for asynchronous as well as synchronous
We can also use JK flipflop..with J=K=1
@@harvey2355 For asynchronous u need to use jk or T fliflop..but for synchronous u can use any
@@ganitacademyengineeringeng4153 u r giving the reply but not admin great to see such people like you
there is an error here, when 001 input, clr will happen
Sir snd me your pen collection I like it 😂
Mitsubishi ball point pen
Thank u sir
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very helpful....thank you
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Best explanation
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can you please help me i need to design n-bit sunchronus counter please help me
Go through my video on synchronous counter
Excellent explanation.
Love and happiness of students is my ultimate goal, God bless you 🙏, keep learning and keep progressing.
So if it changes to any other module counter the circuit diagram changes right?
Yeah
5:05 ..Sir please tell Me..What is LSB and MSB
Most Significant Bit is MSB and Least Significant Bit is LSB
Sir make video on logic families... please!!!
I will definitely make it but it will take some time.
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Thankyou sir .
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For modulo 6 counter we should not take 1 1 0 state.we should stop at 1 0 1 and take clear accordingly???
It will not take 110, it will clear FF at 110
@@EngineeringFunda but unless the state is 1 1 0 how will the clear NAND Gate take it.?
@@vimala8508 state will go to 1 1 0 but as he goes to 110 the clear will do his job and make the output 0 0 0 if we make it for 1 0 1 then it will not count 5 instead of 5 it will give 0 0 0 that's why we take 1 1 0
@@yashkataria2992 thanks