How Semiconductor DRAM Went 3D
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- เผยแพร่เมื่อ 16 ธ.ค. 2023
- Note: I should clarify that the first Intel 1103 was not a Dennard 1-transistor design. It had 3 transistors, and eventually hit the 1-transistor Dennard design in the 16-kilobit generation.
A second clarification: Hat tip to Jonathan M., who pointed out to me that DRAM soft errors are now found to be the result of radioactive elements in the packaging, not cosmic rays. Cosmic rays seem cooler though imo, ieeexplore.ieee.org/document/...
Bonus points if you can tell me how the semi-industry learned tantalum deposition.
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In 1980 I was part of a team tasked with figuring out how to make 64K drams deal with the stray radioactive particles in the packaging materials. At that time 16K bit (bits nor bytes) memory chips were in production.
The 64Kbit memory chip was ramping up and it was quite a challenge.
It's amazing how things have progressed.
you always wonder how it happens, but somehow it keeps progressing. I'm a trained EE and you always think the tech is tapped out but it's not.
When I see a video about IC production now it seems like science fiction to me compared to the way it was when I started.
Then the first IC's had only a few gates on a chip and one flip-flop on a chip. @@stachowi
Wow working in this field in the 80s must have been quite the experience!
@@TheOnlyDamien Absolutely. My perspective on how fast things run is forever contaminated by starting on 1MHz CPUs. You used to be able to listen to your code run by using an AM radio set between stations. Everything just smokes today.
bob456fk6
Hello Bob,
You worked for that Navy, convernement, shielding them, you knew what you were doing ?
For us it was just memory, we never cared how to address it, lower levels of the OSI model, we only needed volatile storage that was fast enough to handle data, 500 ns ?
They tend to do the crazy stuff first with memory. The fact that it is generally an array of small circuits makes things a bit easier than more complex circuits like the SOC. FLASH is another quite interesting area.
It's like building software then, the less you do the more you *can* do.
Ohh the rabbit hole of Multi Level Cache NAND cells and their analog way to store bits, I would love an Asianometry video on this
"Branch Education" made a beautiful video about how exaclty DRAM works, with the precharge, opamps, etc.
branch education is PRIMO.
I was very active in the late '70's with homebrew computing.
For Do-It-Yourselfers the static RAM was definitely the way to go at that time.
Home memory systems had only a few Kbytes at that time. Static rams were still affordable for typical home computers.
Drams required critical timing that made them much harder to use.
A joke in the late '70's:
>> customer: What's the difference between static rams and dynamic rams?
>> clerk: static rams work, dynamic rams don't. 🙂
Yes, it increased complexity for hte benefit of miniaturisation. 1 vs 6 transistors is a hell of a lot. SRAM still has its uses though and has become much cheaper with the die shrinks. The RP2040 for example has 264 kByte SRAM, and with its nifty little state machines (PIO), that $4 thingy is pretty darn powerful. It can sustain data rates up to 360 Mbps, enough for DVI transmission!
I recently purchased some low-cost DDR5 SO-DIMMs, and each DRAM chip on it holds 16Gb. That's 16,777,216 times what the Intel's original 1kb DRAM chip held. In fact, the newer chip actually holds more bits for on-die ECC. That's close to 19 million times the capacity in these tiny button sized things! Crazy!!
That’s exactly how I feel holding a 1TB microsd card… the thing is the size and thickness of my pinky nail and yet holds 100 times more data than my first hard drive, accesses the data multiple times faster, and uses orders of magnitude less power. Blows my mind sometimes.
catsspat
So Dimm it is, small outline alternative on a smaller formfactor, the same.
My Elitebook has 2 So slots, most fancy ultrabook models have it soldered on the board, one 16 Gb DDR 4 chip on a slot, able to do 2 X 64 Gb ma.
HP EliteBook 830, love it, easy to upgrade all parts, wifi, G5 telefoon network, and fast DDR 4 too, 3200, it's 2023 now !
@@einsteinx2 I also always compare chip size to my pinky nail, it's nearly exactly the size of a standard (flash) memory die.
You can get 32GB modules of DDR4, 4 times what DDR3 topped out at (8GB). As he says, at a goal of 4 times the density per generation, I expect DDR5 are, or will be, available in 128GB modules. And for sure, microSD cards are a crazy piece of magic, they blow my mind. I've been buying 128GB USB drives lately for $10, that is the size of my first SSD, which cost probably 30 times that amount, now I'm using these $10 128GB drives just to play lossless music files in the car, where I can almost have an entire library of music on a single device. RAM is so cheap, not only do I use a RAMDisk, I look for other ways for windows to eat up RAM, never close apps, keep them 'cached' etc
@@minus3dbintheteens60 I think the largest DDR3 module available via normal channels was 16GB, I have two of them in my Intel 4690K rig from 2014.
Loved this - as a memory R&D engineer, it’s interesting to see how they addressed past scaling concerns and how we continue to have scaling challenges as well - especially with those pesky capacitors!
Do you do Dram, or Dram and flash?
yeah,
Addressing the physical address we did in the old days !
Writing code how to address it.
I still can't get over how he says SRAM correctly yet pronounces DRAM as one word 😭
Just don’t mention ARF to him :)
th-cam.com/video/BAmbwS3Sf3w/w-d-xo.html
I still remember everybody saying D-RAM like that.
Duh-RAM
Jon is trolling his viewers.
This started quite a while ago.
Personally it just amuses me.
Upper limit = tunneling quantum effect
5th dimensional
I had the same exact thought. mainly because my wife's uncle Michael Woolf did his Phd on quantum tunneling at Berkeley CA.
Then, utilizing quantum mambo jambo to store more data
Binnig and Rohrer were awarded the Nobel Prize in Physics in 1986 for their discovery
I remember that as a kid, i was reading what they did, but now i do understand what they did, i could have discovered it myself, this is the base of how we develop algorithms for designing CPU.
It's Muons, not Alpha particles swirling 12:01 around in huge numbers.
Having done NIR single photon spectroscooy using early CCDs with 12um CCD structures almost 30 years, ago. It was only possible by applying some rigid statistics. Eventhough, Muons caused a huge number of bit flips, which ruined many measures.
Frankly, I wonder how they manage to make chips work since then.
I.e., there must be a insame amount of error correction going on in chips, because Muons statistically often hit multiple neighbouring channels, and cause electron showers.
I think they do this by having neighbouring bits be part of a seperate ECC "cell". I.e; bit 0 is not physically followed by bit 1
Just to be precise, a single muon decay always spawns a single electron, together with a bunch of photons and an anti-neutrino. Preservation of charge, ya know? But I also understand it can ram a bunch of electrons out of their orbits and excite the atoms, before it decays. That's probably the electron showers you refer to.
@paulmichaelfreedman8334 Yes, in deed, for that's how the photo-responsive cells of a CCD chip work. Of course, conservation of energy applies, and all other conservation laws of elementary particle physics apply, too. The whole point is that the passing/decaying muons caused transfers of showers of electrons of the semiconductor under the influence of the CCD' operating voltage into the single cells of the CCD chip, thus ruining the measurement completely, enforcing the application of some nifty statistics to identufy and exclude the hit cells from the spectrum that I measured, back then.
Usually, the NIR photons were meant to cause the electron shower into the CCD cells.
My assumption was that memory cells were in a Goldilocks zone of size where these high energy particles could have outsized effects on memory, and we've since moved on to sizes too small for the effects to be meaningful. But I could be completely off base. I hope he covers these effects in future videos.
yeah i wondered about that, because although alpha particles are the deadliest they are also the easiest to block, unlike gamma radiation. Paper or even human human skin is supposed to stop it, of course if a bitter regime puts it in your tea tough luck...
Just one note: what causes bit flips are not alpha particles, as their decay length in air is just a few centimeters, and so those produced by cosmic rays never reach the surface of Earth, but rather muons.
The alpha particles in 1980 were coming form impurities in the molding plastic. They had to figure out how to purify the molding material to a greater extent. In the meantime, they put a tiny piece of kapton film over each chip to shield it.
The alpha particles are made in the chip by neutron-alpha reactions with the boron-10 used for doping the silicon. The solution is to use depleted boron (Boron-11) instead of natural boron.
I know it's a colloquial thing, and language accent can also affect pronunciation.. But every time he said "dhrahm" as a single word, my brain misfired
Been in the IT industry since the mid/late-90s and I can't recall ever hearing it pronounced any way other than "Dee. Ram.", two separate words. In the beginning of this video he pronounces "S-RAM" that way; "S. Ram." Wonder if it's just a reading-while-exhausted on the 5th-take, kind of thing?
The amount of work put into these pods/talks HAS to be incredible, even if only considering the time spent on research.
MUCH respect for what you do here bud, truly. Love the show :)
No it's a simple to implement "it will drive engagement in the comment section" thing which in turn improves ranking in YT's algorithm so the video will be more likely suggested to other viewers. Easily gives a predictable baseline of 10-20 comments per video.
You're a great storyteller, I thought for sure trench designs would be picked! 😅 Really, you bring out the continual challenges that were not at all obvious how to overcome at the time.
Instead of going through all this trouble , they should have downloaded more RAM .
I really hated the 1103 chip, so many supply voltages and all the row and column pre-charge signals had to be generated externally. What a pain!
They were a pain, especially for hobbyists.
Static rams were very easy to use and for a few Kbytes the cost was not too bad.
I was working with C1103s on video memory boards in 1974 for Computer Optics in CT. What a memory jog! Another great anthology, thanks!
Every presentation on this channel is nothing short of excellent.
If TH-cam has recommended this channel to you, you likely have excellent tastes.
DRAM reads are not destructive like core reads, they simply rely on the gate charge to keep the bit transistor on when you look at it. Refresh is needed because you can never get leakage current to zero so after a while all the charge bleeds out. We saw this in an error in cell phone code where the self refresh was not enabled in time when the proc went to sleep so the memory just bled out and the phone crashed: For standby, the proc was no longer reading or refreshing memory so the chips had a commad that allowed them to do that independently.
I was in Dram manufacturing industry in early 2000 and you are quite accurate about the structures. But i had left the industry for more than 10 years. The last manufacturing process i recall was HSG trench (vertical above gate on ILD).
Industry also needed to move away from lead in solder stacking the memory due to higher durability.
At high density stacking alpha particle admission by the tin. Necessitate materials development to low alpha tin to prevent bit flips
Logic transistor R&D: well replacing the gate designs is very hard, we only tried it twice *sobs*...
Memory transistor R&D: OUR GEOMETRIC MORPHOLOGY IS WORTHY OF ELDRITCH MYTHOS
There's a great RadioLab episode called 'Bit Flip' which tells grim stories of cosmic rays flipping bits with deadly consequences! 👍😎🎄
This documentary is your best work by far ❤
Fusion of electron microscope images and explanation is something else, I’m learning physics more than business
Wow what a development saga. As someone involved in electronics since the mid 1970's the massive increase in memory capacity is mind boggling.
Again and again a fine Mix of complex interesting Themes "easy" presented
Respect for the weekly Perfomance !
Thanks !
great informative and well researched video! As always! You do an amazing job of explaining the details!
Just posted this comment to the Overclockers Australia forums where I spend an awful lot of my online time:
"You guys watch Asianometry right? If you don't, check him out.
Taiwan-based and has an excellent line into semiconductor-related stuff specifically (works in the industry I believe), but his geopolitical analysis stuff is also pretty well-researched and detailed.
I also like his rather dry delivery and sense of humour. Recommended. "
as always I learned a lot and I'm keen to go deeper in next episode!
I would love to see you cover SiC for memory usage, it’s what I studied in university and the thermal carrier density was astronomically low, like 1 in the volume of earth at any one slice in time. I remember calculating residence times in the order of thousands of years. I wonder where that ever ended up, I’ve been out of the game too long.
Texas Tech University has a group researching SiC in use for high voltage high current stuff. I'm not involved in them so I don't know much besides that.
> Assuming Arrhenius type dependence of the charge
retention times on temperature, the high-temperature
results can be extrapolated to mom temperature. This
provides estimates of the charge-retention times at room
temperature. In the case of 4H-SiC, the room temperature
retention times were 10" years for the sandwich process
and IO9 years for the diluted N20 process. The sandwich
process on 6H-Sic produced a lower value of IO6 years. As
these results illustrate, the charge-retention times are
strongly affected by the gate-oxide processing, which
indicates a strong dependence on the interface-trap density.
This conclusion has been confirmed in a subsequent study
of the generation rate [30], showing that the creation of the
inversion layer is due to surface generation whereas all
other mechanisms (including bulk generation in the
depletion layer) are negligible.
> This limitation to the capacity increase is the same for
both, the volatile DRAM on Si and the potential
nonvolatile dynamic RAM on Sic. A very important
advantage of Si-based DRAM, however, is that it is a well
established technology that provides unchallengeable
memory capacity for a given price. The implementation of
the lT/lC based array in S i c would provide the technical
advantage of the nonvolatile dynamic RAM, but at a high
cost. For that cost, it would appear that competitive
applications could be achieved by combining volatile
DRAM with flash memories.
> Therefore, to utilize the unique potential of S i c with
passivated surface for developing nonvolatile dynamic
memories, new cells need to be developed that would
provide increase in memory capacity beyond the level
achievable in silicon technology
From DOI: 10.1109/EDSSC.2003.1283560
New Asianometry, Sam O'nella and History of the Universe?! Woooo! Almost makes me feel like I'm not dead inside.
I share your take on the tremendous effort to secure these technologies. Wow!
Love your videos.
For when a video about the 3D VCache??
Interested in this aswell
favorite channel consistently!
I love the fact that you are just casually bridging the gap in understanding of these advanced topics for our generation.
I remember buying ram at a dollar or more a MB- spending my rent money and then popping the ram trying to over clock it. Ahh good times
My first 16K came at a cost of $279. I think they were 350ns chips.
Finding bad chips in a repair was fun.... Just use your hand. The chip that gave you the 2nd degree burn needed replacement.
We paid $100/MiB for our 386 machine (Used 4MB and could run Windows). Back when they did a full memory check at every cold boot, so you turn it on before going to make your pot of coffee.
ICs have always been about shrinking the electronic component to the smallest it can possibly be. Sure, transistors are what comprise processors, but capacitors have to be even smaller for ram.
Damn that's some impressive Science, Invention, and Engineering to make DRAM keep getting better.
‘Condenser’ is basically the German phrase for Capacitor. “Kondensator”
I'm a scientist and yet... I understand half of your videos. And it somehow makes me feel smart.
Well every scientist would feel dumb on things that are not in his/her field of expertise. So this is normal, though I would have thought you would've known this. If I may ask, what would you consider as a "scientist"? A Bachelor, Master or Doctorate? Or just someone who works in RnD?
@@hyeon-seoyun6940 It is mostly that this industry is so alien to me. I'm an enviro scientist, which makes my basics background a generalist's. It involves pretty much all "pure" sciences, plus a small ammount of engineering. I often find enough overlap to follow a PhD talking shop on most pure sciences, and even with astronomy and computer sciences (lots of remote sensing, programming, modeling, etc). But not here. This is a lot of engineering plus a bunch of other specialties, and the overlap is surprisingly low. And yeah, I consider a professional that is able to conduct academic research on his own (as in, unsupervised, not without an institution) a scientist. The number of degrees is not that relevant in practice, altho most would be PhDs or Masters.
And i though processors were complicated until watching this... this is absolutely insane how they build detailed mega-micro structures like this
So what was Rambus RDRAM? I only remember the hype and marketing, but not much else about it. DDR ended up completely taking the market and RDRAM ended up as the Betamax to DDR's VHS.
I'm in the same boat as you mate, I remember little about the details other than AMD throwing some weight behind the tech in the early 2000's for a time.
I was much younger and not as clued-up back then but if I remember rightly, RDRAM theoretically had the potential to become an exciting step forward but it simply never gained enough market traction in a very Intel-dominated era.
I'd love to see an Asianometry video on Rambus!
RDRAM used a different module and memory controller design, which allowed for higher clock frequencies, but was also more expensive, partially because of license fees from Rambus, partially because other DRAM makers conspired and sold their chips for below production costs to force RDRAM out of the market. So at some time, when DDR-SDRAM managed to narrow the gap to RDRAM, the latter was just too expensive to justify the slight performance increase that the faster RAM gave to real-world applications, so RDRAM was forced out of the market.
I think the reason why it is not covered in the video is because the video is solely about DRAM chips, and mainly about capacitor technology. RDRAM didn't use any different technologies on the chip-level, it just used high-end chips that where otherwise used in video cards and some video game consoles.
@@rfvtgbzhn Interesting, thank you!
I also can't get over his way of pronouncing anisotropic, it's an-isotropic. Great video though.
awesome video !
Love seeing DRAM makers getting some respect for their mind-bending process technologies. Unfortunately, DRAM often gets short shrift because it’s seen as “lagging” in process technology behind the leading edge logic guys, because they’re not making, as you mentioned, transistors like FinFETs, and because DRAM is a commodity where cost is king.
However, as you explained, DRAM first went to 3D capacitor structures, which greatly increased manufacturing complexity. But by the mid-2000s (5+ years before FinFETs became a thing), DRAM makers also started making 3D transistors as well. The Access Device (AD) transistor used to be a planar nMOSFET. Hundreds of ADs would be lined up next to each other, then the Wordline was a piece of metal (or poly or whatever) that was laid over all of the ADs in the same row, forming the Gate of all AD, such that when the Wordline is activated, all of the ADs connected to that Wordline are simultaneously turned on.
In logic chips, the most important characteristic of a transistor is the switching speed, followed by things like on-current and off-current. In a DRAM Acess Device transistor, the single most important characteristic is minimizing rhe off-current (or I-Off), because that is what prevents capacitor leakage. So, by the mid-2000s, the channel length of the AD was getting to be too short, and I-Off couldn’t be kept small enough to prevent capacitor leakage. Similar amounts of leakage in a logic chip was “fine”, because it only increased power consumption slightly. But in DRAM it was devastating because the whole point of DRAM is to store data without forgetting it.
So, that’s when DRAM Access Devices went 3D. But, they did the opposite of FinFETs, in that in DRAM, the Wordline was buried down into the silicon into a trench. Unlike the “trench capacitor”, which was actually just a punched out hole in the Si, buried Wordline is a true trench - a long, skinny, U-shaped trench filled with metal, etched into the Si between the Sources and Drains of the ADs. Hundreds of ADs are formed on a single buried Wordline, and of course there are millions of Wordlines per chip. Now with a buried Wordline, the channel that forms between the Source and Drain has to form under the same Wordline, in a long U-shape going through the silicon substrate. In the manner, the lateral distance between the Source and Drain can continue to shrink (which is required to continue die-shrinks), but the “effective channel length”, which is the total length of the channel as it wraps around the buried Wordline, can remain long. This long channel is what’s critical in stopping leakage when the AD is turned off. It’s also one reason why the switching speed is the AD is slow, relative to logic transistors.
Anyway, you could do a whole separate video of the evolution of DRAM Access Device transistor technology. The combination of incredibly complex Acess Device and Capacitor technology are what allow us to have monolithic 4GB DRAM dies now, still still latencies less than 20ns
Wow this is so out of my reach. But still thank you for this post.
Fascinating! I’m sure everyone knows how a flip flop based storage device works. Thanks!
OMG, 112 volt memory capacitors. 😅
Duke Nukem Atomic Edition Queen (last level) is designed to fill the golden chips with Physx instructions. The chip exists in new laptops, and it is empty. The game level acts like a flight simulator, ascending and descending. Using steroids you can speed up the virtual plane. When the frameskip stops, you fixed the video card.
“Shrinkage got harder”
superb video.
Jon, it would be great if you could conduct a deep dive in Si Super-Junction MOSFET technology. Specifically considering both TFEG and MEMI construction methods
Image a world of DIMENSIONS. Expand in different coordinates and enjoy the SPACE that is in all directions. It is love.
THIRD
DIMENSION
We are 3D it's real and we walk in the 3rd dimension, and think in the 3rd dimension. Love to love, love to be 3D.
Lay off the shrooms, Gregory
What a wild ride of a comment
Wow, that was very interesting. And make me wonder about flash memory cells, how they look, especially 3D NAND.
Flash memory cells are fascinating in their own right. But, at the single-cell level, Flash is simpler because it just has one transistor. It’s a modified transistor that has, basically, and extra gate (where the charge is trapped for data storage), but it is just 1 transistor per bit, whereas DRAM is 1 transistor + 1 capacitor per bit.
But like you said, 3D NAND is where it gets cool. Since it’s just 1 transistor per bit, the NAND makers have been able to rotate the transistor vertically, then stack hundreds of them on top of each other. That’s not possible with DRAM with the (relatively) huge capacitor
we must not forget who started this all, the scientist: Micheal Faraday.
4D lets not forget spacetime
Thanks!
Nice! Asianometry is a fellow "pronounce all acronyms as if they are a single word at all costs" enjoyer
Makes me wonder what exotic materials they'll develop in the future?
Jon! I have an interesting idea for a new video. The History and Development of the Modern IHS. This has interested me for a little while now.
I get that there is probably a lot of red tape behind patents of each tech. but wouldn't the logical step be to combine the cylinder cap tech with the substrate-plate tech to make it easier to fabricate while also reducing the real estate needed for trench technology?
I understand none of this. . . . but I feel smarter for having watched it.
How does this relate to current research around resistive memory?
Historically ? We understand how to address it, allocate it.
3D space you meant, beyond one and Zero storages ?
resistive memory !
At 5m25 the green arrow should be pointing down (you try to shrink d)
What do you mean by memory as commodity?
Could you explain why optane has been abandoned ?
Optane was not a DRAM process. It was a non-volatile phase-change-memory-type product. It was envisioned/hoped to be a replacement for both DRAM and Flash, where systems could finally have a single large bank of data that could be used for both storage (because it was non-volatile, so it could replace Flash) and memory (because it was fast, so it could replace DRAM). But, turns out, it was 1) not fast enough to replace DRAM, and 2) not cheap enough to replace Flash. So, instead of simplifying the memory hierarchy, Optane made it more complex, because it added another layer of memory, but systems still needed DRAM and Flash/HDD anyway
Wow a 120 volt bit!
I have no idea why I watch your videos
Thinks your local electrician inventor, between jobs: Hey, I would make storage and switch as the connection lattice itself.
Who needs interconnected nodes when nodes themselves are the interconnect. Nature does it all day. Think DNA.
I just heard recently that Huawei has just released its 5nm chip. Could you make a video explaining this new progress in China? Thank you
How can zero be refreshed?
Daaammnn DRAMuel...
A few dozen milliseconds is not as few. That's an eternity in computer timing. A single 60 FPS frame is almost 17 ms.
Wait, that doesn't sound quite right. K is the Coulomb Constant. It is dependent on the dielectric constant, epsilon, but K assumes a vacuum, therefore setting it at 9e9.
But that's just a nitpick. Well done over all!
They mean the relative dielectric constant, which is in relation to the vacuum dielectric constant and denoted by kappa, which is sometimes replaced by k in electric engineering. So for vacuum, k=1. Barium titanate has one of the highest values of k, up to 15,000, however it probably can't be used in semiconductors, at least not with current technology. It's used in some high-end capacitors, normal capacitors use cheaper materials which have a k in the range of 20 to 70.
@@rfvtgbzhn ah, that makes sense.
I imagine that at some point we will not have flat CPU/SOC/RAM chips but we will transfer to 3D computing blocks. But there is probably a very obvious reason why that would not work
Yes. Heat dissipation.
For flash memory they already use multiple layers stacked one over another. New products have over 200 layers. Also AMD Ryzen X3D cache, one layer of cache on top of compute module. For Ram there are HBM memory, also stacked.
Maybe Ryzen 4c cores also are kind of stacked, they manage to out same number of transistors on smaller surface, so probably more components overlap.
Volume, therefore thermal mass, grows as a cube of size. Surface area for dissipation grows as a square. The lines cross pretty fast and you can’t cool off.
My physics professors would argue that the equations for capacitance is:
F=ma
2:11 something went wrong
It's not "a-niso-tropic", it means the opposite of isotropic, so it's "an-iso-tropic". Hope that helps!
Came here to say this, thank you!
E = MC2😂. How did that make me laugh
The "high-k" dielectric don't seem that impressive with a k of (according to this video) 25 maximum, compared to for example barium titanate, which can have up to 15,000. However I guess the materials that can be used in DRAM are very much limited by the manufacturing process.
Who is this Semic Onductor?
🎯 Key Takeaways for quick navigation:
00:02 🧠 *Evolution of DRAM: The video explores the journey of Dynamic RAM (DRAM) from its 2D structure to 3D structures and beyond, highlighting the challenges faced in scaling memory capacities.*
03:13 🕹️ *Shrinking Memory Cells: Memory scaling involves shrinking one-transistor memory cells, particularly focusing on the challenge of shrinking capacitors due to limitations in capacitor size and capacitance.*
08:17 ⚖️ *Trench vs. Stack Capacitors: Memory makers faced a dilemma in choosing between stacked and trench capacitors for the 3D structure. Trench capacitors offered advantages in density but had challenges in manufacturing and data integrity.*
14:47 🌐 *Hemispherical Grain Structure (HSG): The introduction of HSG in stack capacitors during the 64 megabit and later generations was a critical innovation, enhancing capacitance values and providing a competitive edge.*
15:41 🔄 *Innovations for Increased Density: To increase DRAM density, the industry introduced cylindrical capacitors in the late 1990s, leveraging advancements in lithography machines. Exotic High K dielectric materials, such as tantalum pentoxide, were also adopted for further scaling improvements.*
Made with HARPA AI
Interesting! In addition to the time codes, it goes a bit farther than summaries in the "Ask" experiment feature on TH-cam. 😎✌️
You got me with the e=mc^2 I was watching an was dang that it .....wate a min 😆😆😆 good one 👍👍👍
Also the WL/access transistor is 3D since 90nm technology. Samsung was 1st with RCAT. Later Qimonda completely stucked with Trench revolunized DRAM, switching to stacked but also inventing the Buried Worldline. With no money to ramp they could not get benefit out of it. The concept is sill used in todays DRAM. By the way playing around with all the high k materials Qimonda guys found a HfO phase which is ferroelectric and is today basis for the development of ferroelectric memories.
All this tech so Windows can use memory less and less effectively
Babe wake up...
I live in Brazil.
Cool story, bro.
ayyyyy
Ayyyyyy
For any old heads worried, we get one DRAM in
This is a but too high level for me, I’m just not smart enough to understand
e=mc^2 --- HAHAHAHAHAHAHA!!!!!!!! I love it.
Anisotropic, You Rock Freind
i find it weird when people pronounce "dram" as a word. i and everyone i know, say dee ram or ess dee ram. etc. not "dram"
That’s how you say it? It’s pronounced dee ram
Dee RAM, Ess RAM, PeeEss RAM, Eff RAM, EssDee RAM, and now we have Emm RAM too.
I wonder if someone is checking the accuracy of your videos. I'm a business teacher,and I'm hearing everything you say for the first time, I have no idea if you have any inaccuracies. Do you have any critics on TH-cam and have you listened to their work? Do they (if any) give you useful feedback?
There are some weird pronunciations but nothing that’s outright wrong (see: anisotropic is not pronounced like a-neeso-tropic)
Ok I did find one outright error: he claims alpha particles come from cosmic rays, but that’s muons. The alpha particles in question come from the manufacturing materials.
Also nobody pronounces dram as “dram.” It’s “dee-ram.”
15:25 You ment to say gigabit and not gigabyte? Its an 8 times difference 😅
too many ads, thumbs down
This was a hell of a ride🫡 I loved every second😎
Dynamic RAM. I see what you did there. 😏