Without your videos, I would be questioning my future as an EE major because of how hard my professor makes the material seem. You manage to make everything seem like common sense especially when you try to relate to real world examples. The world and more specifically the realm of teaching needs more people like you. For this, I thank you.
I appreciate this lecture. Having designed switching systems in industry, this is a great refresh/reinforcement of the basic principles upon which many systems act, with either an active high or active low Set/Reset channel switch, be it fiberoptic, ethernet, etc. It is great to see that it is also completely done in the computer, as opposed to the traditional chalk/whiteboard. Many thanks, Jim,for your time & for making this freely available to all!
youtube is blessed to have Jim Pytel's channel..........u make things really simple....n yeah those subtitles were really useful........thanks a million!!!! hey please keep uploading lectures on electronics......thanks again..:)
You are godsend sir. You have single-handedly taken one of the most confusing classes I am currently taken and made sense of it. I learned and understood more watching this one video than I have from a week's worth of classes. Thank you.
Your videos are excellent! You are a very clear teacher. The way you carefully walk through the timing clarifies the whole concept in a way that a static table cannot. I sometimes have my classes watch your videos.
just started electrical engineering tech, had no idea about any of this stuff... watched some of your videos and i feel i have a pretty good handle on it now, thanks jim :) you have been a big help
SnR latches are a very tricky thing to figure out. Was all over YT looking for the best explanation...Pytel's the best and most comprehensive I found. Thanks a milli. Love from Nigeria.
What an amazingly phenomenal explanation!!!! unbelievably outstanding job with all the analogies etc. Why couldn't we have a teacher like you? Sheeez! ...I'm taking a digital design and computer architecture course at UC Berkeley and have to repeatedly come back to your videos to understand things properly!
You saved me. I've been completely puzzled by this lab exercise for a whole week and you just made it all make sense now. Thank you. Really. Oh and the Ewok joke was good ;)
Thanks for not assuming everyone would immediately understand what latch would mean. Question. I have a small dc motor, which when the polarities are reversed, the rotation of the motor reverses, which is what I want. Is a flip flop the best way to control the reversal of polarities? Does 0 equal ground? Thanks!
sooooo.....at power up, some sort of delay to the "set" must be implemented so that reset in high first to guarantee "Q" is at logic "1" or is there some sort of built-in system for this.
***** This is probably a bit late for this comment, but he didn't really "derive" the Q=1 and Q'=0 from anywhere, it was a given variable. He didn't really show that it was a given in the first example but he did in the second one with the timing diagram.
Terrific sir, you are awesome. Btw at 24:30 Q should be the output of NOR gate with R as input. No offence by any-means. Keep up the good work and Thank you !
You said that when you hit Set AND Reset at the same time, you get an unpredictable Q output. Does this mean you can create a RANDOM bit of data? Maybe not *truly* random, but at the least, very unpredictable?
what kind of drawing program are you using. I am in EET 121 and we are going over latches this week. it was confusing me if you just have one input on a two input gate it will not work. So you have to start with initial conditions, otherwise it will not work. otherwise you cannot get any output to Q ever. the gates will never work unless you have initial conditions
I guess it's because just using 2 NOR gates will be cheaper than using 2 NOT and 2 NAND gates. Even though a NAND gate in the IC can be used to implement a NOT gate function to substitute an actual NOT gate, ultimately still using only one NAND IC chip, 3 gates will have to be used in one IC, as opposed to only 2 if using NOR implementation.
So an SR Latch is always an active low? and i know when in set mode Q = 1 and reset mode Q = 0 but does that also mean that S = 0 for set? and R = 1 for reset?
Because this is the NAND version of the SR Latch (instead of the NOR version) it uses S-bar (not S) and R-bar (not R). S = 1 is still set, causing an active low of Sbar (not S) = 0. R = 1 is still reset as well, causing Rbar (not R) = 0
@baharsahin Hi I'm French, There is no differences, you just invert the position of R and S (R in front of Q and S in front of Q prime). You start with S,R = {0,0} and you read the NOR's truth table (only 0,0 makes 1). The set and the reset have the same impact to Q. Actually, the NOR's truth table is the same than NAND's one if you change 0 to 1, and 1 to 0.
so what would actually happen if you set them both to zero in practice? theoretically it wont work because it violates the logic law, but what does it actually do?
man i have a question. why do you use not s and not r for input? you can totally just switch the two inputs since s and r are complements of each other.
Isn't it amazing how clear a community college professor can make this when my State university professor couldn't teach us how to wipe our asses? Thank you Jim.
If you wanted to make an active high SR latch with the current circuit configuration couldn't you just stick an NOT gate in front of the S and R inputs?
I may have missed links among ur videos... TH-cam doesnt really provide any better navigation tools.. Great video though, I may stop showing up to class =)
Those who liked this video...you guys are not study enough....Jim definitely did a great job on the explanation, but there are two other very basic tables beside the timing diagram which depict the relation between the change of state and output. Where are the two tables?
Without your videos, I would be questioning my future as an EE major because of how hard my professor makes the material seem. You manage to make everything seem like common sense especially when you try to relate to real world examples. The world and more specifically the realm of teaching needs more people like you.
For this, I thank you.
this is my first youtube post ever... I just sat in a class for 8 hours with a blank stare and watched this video and get it... Thank you so much.
I appreciate this lecture. Having designed switching systems in industry, this is a great refresh/reinforcement of the basic principles upon which many systems act, with either an active high or active low Set/Reset channel switch, be it fiberoptic, ethernet, etc.
It is great to see that it is also completely done in the computer, as opposed to the traditional chalk/whiteboard. Many thanks, Jim,for your time & for making this freely available to all!
youtube is blessed to have Jim Pytel's channel..........u make things really simple....n yeah those subtitles were really useful........thanks a million!!!! hey please keep uploading lectures on electronics......thanks again..:)
You are godsend sir. You have single-handedly taken one of the most confusing classes I am currently taken and made sense of it. I learned and understood more watching this one video than I have from a week's worth of classes. Thank you.
This is an excellent video. The explanation and voice clarity is really good.
Your videos are excellent! You are a very clear teacher. The way you carefully walk through the timing clarifies the whole concept in a way that a static table cannot. I sometimes have my classes watch your videos.
just started electrical engineering tech, had no idea about any of this stuff... watched some of your videos and i feel i have a pretty good handle on it now, thanks jim :) you have been a big help
SnR latches are a very tricky thing to figure out. Was all over YT looking for the best explanation...Pytel's the best and most comprehensive I found. Thanks a milli. Love from Nigeria.
you explain this concept so clearly !!! u should win a award for explaining....
What an amazingly phenomenal explanation!!!! unbelievably outstanding job with all the analogies etc. Why couldn't we have a teacher like you? Sheeez! ...I'm taking a digital design and computer architecture course at UC Berkeley and have to repeatedly come back to your videos to understand things properly!
Thanks for the video! I'm a college student at a relatively rigorous college and I found this very helpful. Keep up the good work.
Oh, this is very nice, and helpful. Thanks for putting it up! I'm going to remember your channel for later.
You saved me. I've been completely puzzled by this lab exercise for a whole week and you just made it all make sense now. Thank you. Really. Oh and the Ewok joke was good ;)
26min with you made me understand so much more than 90min with my teacher
@20:00 Most enlightening 2 mins I've had in this material I've been learning for over a month
Thank u very much Jim, you elaborate each and every thing which i like about u.
great job man. I didn't know what latch meant until you explained it.
ty so much! you made this concept so clear for me I was able to understand my teacher's slideshow(without your explanation i was puzzled) so tytyty!
acually.. it is the best video ,, i have ever heard
thank u so so much
Namaste,
Thankyou- all the way from Nepal !!!
Thanks for not assuming everyone would immediately understand what latch would mean.
Question. I have a small dc motor, which when the polarities are reversed, the rotation of the motor reverses, which is what I want. Is a flip flop the best way to control the reversal of polarities? Does 0 equal ground? Thanks!
Amazing videos keep up the good work.
this is the best tutorial ever
thank you so much! more tutorials please! especially on edge triggering bistables. i don't really get it. where do we apply all these things?
Thanks!
Nice! Thanks for the explanation. My prof just has us building flip flop counters without telling us the how/why/what. This'll help!
great job; Loved the video
absolutely couldn't agree more. thank you so much
sooooo.....at power up, some sort of delay to the "set" must be implemented so that reset in high first to guarantee "Q" is at logic "1" or is there some sort of built-in system for this.
but how do you enforce that initial "set" condition where Q=1 and Q'=0? how can you drive the outputs to something?
Yes, that exactly what I want to know how do you drive the initial conditions in the first place?
***** This is probably a bit late for this comment, but he didn't really "derive" the Q=1 and Q'=0 from anywhere, it was a given variable. He didn't really show that it was a given in the first example but he did in the second one with the timing diagram.
Oros Abaddon
Okay, that makes sense. I finally understand. Thank you. :)
thank you for the starwars joke! this video is awesome!!
Thank you Jim!! It's finally clear to me now. :)
Terrific sir, you are awesome. Btw at 24:30 Q should be the output of NOR gate with R as input. No offence by any-means. Keep up the good work and Thank you !
i get that joke and did it all for the wookie. Thanks for the good vid, i need help to pass my FE.
you are excellent,, got everything u said ,, brilliant
In my book, it uses NOR gates instead of NAND gates. What is the difference between using NAND gates and using NOR gates in SR latch?
I am straight.... but I love you. THANK YOU SO MUCH FOR EXPLAINING THIS CLEARLY! This video is worth its weight in gold!
You said that when you hit Set AND Reset at the same time, you get an unpredictable Q output.
Does this mean you can create a RANDOM bit of data? Maybe not *truly* random, but at the least, very unpredictable?
what kind of drawing program are you using. I am in EET 121 and we are going over latches this week. it was confusing me if you just have one input on a two input gate it will not work. So you have to start with initial conditions, otherwise it will not work. otherwise you cannot get any output to Q ever. the gates will never work unless you have initial conditions
I guess it's because just using 2 NOR gates will be cheaper than using 2 NOT and 2 NAND gates. Even though a NAND gate in the IC can be used to implement a NOT gate function to substitute an actual NOT gate, ultimately still using only one NAND IC chip, 3 gates will have to be used in one IC, as opposed to only 2 if using NOR implementation.
excellent explanation...thanks very much for your help
Wonderful..Love your lecture :)
jim do you have any lectures on binary?
@indago9 you happen to have got that from minecraftwiki? :P
omg thank you so much, these videos are amazing! :)
I almost feel guilty paying such good money to go to a University when you have taught me SO much more than my Professor.
So an SR Latch is always an active low? and i know when in set mode Q = 1 and reset mode Q = 0 but does that also mean that S = 0 for set? and R = 1 for reset?
Because this is the NAND version of the SR Latch (instead of the NOR version) it uses S-bar (not S) and R-bar (not R).
S = 1 is still set, causing an active low of Sbar (not S) = 0.
R = 1 is still reset as well, causing Rbar (not R) = 0
@baharsahin Hi I'm French, There is no differences, you just invert the position of R and S (R in front of Q and S in front of Q prime). You start with S,R = {0,0} and you read the NOR's truth table (only 0,0 makes 1). The set and the reset have the same impact to Q. Actually, the NOR's truth table is the same than NAND's one if you change 0 to 1, and 1 to 0.
Thanks you very much for making this video..
so what would actually happen if you set them both to zero in practice? theoretically it wont work because it violates the logic law, but what does it actually do?
Thanks for not assuming everyone would immediately understand what latch would mean.
man i have a question.
why do you use not s and not r for input?
you can totally just switch the two inputs since s and r are complements of each other.
The active low set is confusing. I'm not clear on when you're talking about S or S'.
You are my teacher, because my current teacher isn't very good.
how to get active high nand latch
Isn't it amazing how clear a community college professor can make this when my State university professor couldn't teach us how to wipe our asses?
Thank you Jim.
If you wanted to make an active high SR latch with the current circuit configuration couldn't you just stick an NOT gate in front of the S and R inputs?
Thanks a lot,sir!!!
it helps me a lot thanks :)
u r my hero :D:D:D thank u , u saved ma life
Way too awesome!
thank you so much for this!
I may have missed links among ur videos... TH-cam doesnt really provide any better navigation tools.. Great video though, I may stop showing up to class =)
Wonderful !
never going to look down on community college ever!
wish all teachers could explain like this :)
@Risssshab This is microsoft onenote, i believe
Those who liked this video...you guys are not study enough....Jim definitely did a great job on the explanation, but there are two other very basic tables beside the timing diagram which depict the relation between the change of state and output. Where are the two tables?
Very helpful!!!!!!
THANK YOU SO MUCH. 1000000000 karma points
thanks bro really helpful
why do you us not S & not R instead of S & R, is everything just reversed?
thanks a lot!
I didn't get the 6ft living with 3ft joke :/
I thought the SR Latch was called the RS Nor Latch.
the last logic circuit is not right, you need to switch the S and R for the logic circuit
My mom asked me where i am, I told her I'm hanging in set land.
the Chewbacca defence
Only Bud and Bug light? Kill me already!
Bu 7amood say's Hiiiiiiiii
good
u can do something called "Alt-z" lol dont need the eraser
U -> R : AWSM ,, that's it.
lmaaoo at the joke
nice analogies lol
A7mdo loves LATCHES if you know what i mean ;)
NOPE.AVI
Thanks!