Well ... I have to say, you had me going for a while. Having done this before, at first I was horrified at the complexity of your verilog code. BUT one step after another, you introduced new concepts and changed your code until by the end of the video, it was exactly the way I would expect it to be. Brilliant ... now I have a better understanding of what not to do. Also, (you might have mentioned in your first video): You spent a fair amount of time talking about logic equations and Karnaugh maps. Obviously, an Electrical Engineer needs to understand these concepts. Seems that you were making a point that doing this by hand is tedious. However, in the real World there are tools. Notably, Logisim pretty much crushes this. One need only create a simple text file with inputs and outputs, load it into Logisim, and it instantly creates a logic diagram. That's what I would have done it at least.
Excellent episode! Thanks for this series. Very informative. Just a question. I have noticed that the 4 GPIO pins used as inputs are connected directly to the 5v rail on the breadboard. I thought the GPIO on the FPGA board were 3.3v tolerant. Can you please confirm it? Thanks and keep up the great work!
There is no "5v rail" on the breadboard. There is a rail, and it carries whatever it is you connect to it, be it 5v DC, 25V AC or a 6Hz analog signal that draws a duck on the oscilloscope. In this case, I've connected it to the 3.3v exit from the board, and that's what's fed back in.
I still wonder if I made the right choice to learn VHDL instead of verilog. but back then verilog was too limited in what I needed to do. I've used all kinds of VHDL features like OR array busses and generate arrays of modules. VHDL is very pedantic and annoying, but it can do a lot. I've not looked at system verilog, but in VHDL you could have just added a (0 upto 6) on each line where the LED outputs were being set to reverse the order it goes into the output.
From what I could read, no, that would have required a for (probably generate for) loop. But that wasn't the point I was trying to make. The point I was trying to make was that, with FPGA design, the *requirements* are sometimes subject to programming decision.
Great job! I really appreciate the content you're creating. Looking forward to seeing more on FPGA and maybe some HLS. Keep up the good work!
Amazing! I just got my FPGA dev kit in too! cant wait to give this a go :D
Wow. Love to see FPGA Content !!
FPGA content?? In a series called "FPGA concepts"????
We have standards here!
Keen to watch this and see where we go!
Always a good day when you upload content!
My deepest thanks.
Well ... I have to say, you had me going for a while. Having done this before, at first I was horrified at the complexity of your verilog code. BUT one step after another, you introduced new concepts and changed your code until by the end of the video, it was exactly the way I would expect it to be. Brilliant ... now I have a better understanding of what not to do.
Also, (you might have mentioned in your first video):
You spent a fair amount of time talking about logic equations and Karnaugh maps. Obviously, an Electrical Engineer needs to understand these concepts. Seems that you were making a point that doing this by hand is tedious. However, in the real World there are tools. Notably, Logisim pretty much crushes this. One need only create a simple text file with inputs and outputs, load it into Logisim, and it instantly creates a logic diagram. That's what I would have done it at least.
Logism isn't the only tool. Another tool that does this for you is.... any HDL compiler.
Really nice introductory video! It's a really nice example.
I'm really glad you liked it.
@@CompuSAR I did! I'm keen for the next part, but appreciate these take ages!
Not to mention I need to advance my usual project too. I am going to start making those more "hands on" too, however.
Excellent episode! Thanks for this series. Very informative.
Just a question. I have noticed that the 4 GPIO pins used as inputs are connected directly to the 5v rail on the breadboard. I thought the GPIO on the FPGA board were 3.3v tolerant. Can you please confirm it?
Thanks and keep up the great work!
There is no "5v rail" on the breadboard. There is a rail, and it carries whatever it is you connect to it, be it 5v DC, 25V AC or a 6Hz analog signal that draws a duck on the oscilloscope.
In this case, I've connected it to the 3.3v exit from the board, and that's what's fed back in.
Awesome, thanks for clarifying! It all makes sense.
I still wonder if I made the right choice to learn VHDL instead of verilog. but back then verilog was too limited in what I needed to do. I've used all kinds of VHDL features like OR array busses and generate arrays of modules. VHDL is very pedantic and annoying, but it can do a lot. I've not looked at system verilog, but in VHDL you could have just added a (0 upto 6) on each line where the LED outputs were being set to reverse the order it goes into the output.
From what I could read, no, that would have required a for (probably generate for) loop.
But that wasn't the point I was trying to make. The point I was trying to make was that, with FPGA design, the *requirements* are sometimes subject to programming decision.
We worked so much harder on these in High School... De-Morgan's law, Karnaugh maps...
I take it you missed part 1.
th-cam.com/video/xXZACRtt2lk/w-d-xo.html