They have many mistakes. It's better to take their datasheet and try to do your own calculations based on the internal blocks of device and than only compare the resuslts. Related to their application note/design examples, they are killing the designer work if you just take the formula...
Hi Professor one doubt. To find the gate driver power loss, can we do it in this way. Find the average input power like you mentioned and average out power in out pin. Will the gate driver loss be input power- output power? Am I missing something here?
Exellent Video!, i'm currently working on a brushless motor driver, and we have some issues on the thermal design and power dissipation. this is really hepfull to understand a bit more about the gate driver operation. by the way the precense of ringing on the high side mosfet dough to parasitic pcb inductance may affect the total power dicipated for the IC?
I believe ringing does add power losses, and not only that, it increases the issue with EMI compliance; that why snubber is used, which can lead to higher power losses depending on switching freq for silicon-based MOSFET and size of gate charge, etc.
My goodness what a beautiful and thorough presentation. This was awesome. Professor, do you have any online classes that one could take. Your presentations are so well thought out.
I believe what you explained is correct except at @19:50, I think there is a misconception of power losses for which component. The datasheet indicates that are power losses for their gate driver IC component (quiescent power loss + switching losses), and at @19:58, those gate resistors are exceptions to the gate driver IC component. If we include those power losses from the gate resistors to the gate driver power losses, that is not fair. Different customers may use different resistance values for that gate resistors.
72mW are the quiescent loss, 336mW is the the TOTAL charging loss which is divided between the driver and other resistors in the chain. So including ALL the 336mW as contributing to the temp rise is incorrect. Am I missing something?
I've spent the last week learning about the switching losses from TI's datasheets and I was wonder why it never matched up with my simulations. Thank you for clearing this up!!!!
I was constantly surprised by mistakes in the TI datasheet/app note, nice video.
Indeed. Surprising.
They have many mistakes. It's better to take their datasheet and try to do your own calculations based on the internal blocks of device and than only compare the resuslts. Related to their application note/design examples, they are killing the designer work if you just take the formula...
@@CATA20034 The worse part is that many a times they are giving equations without any explanation
Perhaps the pre-requisite educational standards at TI have been diluted over time.
Indeed
Excellent source of information in this video, by the way. Thank You.
Thanks
Hi Professor one doubt. To find the gate driver power loss, can we do it in this way. Find the average input power like you mentioned and average out power in out pin. Will the gate driver loss be input power- output power? Am I missing something here?
How would you find the output power?
Exellent Video!, i'm currently working on a brushless motor driver, and we have some issues on the thermal design and power dissipation. this is really hepfull to understand a bit more about the gate driver operation. by the way the precense of ringing on the high side mosfet dough to parasitic pcb inductance may affect the total power dicipated for the IC?
I believe ringing does add power losses, and not only that, it increases the issue with EMI compliance; that why snubber is used, which can lead to higher power losses depending on switching freq for silicon-based MOSFET and size of gate charge, etc.
Not really. Thanks for sharing
My goodness what a beautiful and thorough presentation. This was awesome. Professor, do you have any online classes that one could take. Your presentations are so well thought out.
Thanks
Why is PRd set to 0 at 8:37?
It is part of the driver that has been taken into account
Excellent presentation as always.
Thanks Hamid
I believe what you explained is correct except at @19:50, I think there is a misconception of power losses for which component. The datasheet indicates that are power losses for their gate driver IC component (quiescent power loss + switching losses), and at @19:58, those gate resistors are exceptions to the gate driver IC component. If we include those power losses from the gate resistors to the gate driver power losses, that is not fair. Different customers may use different resistance values for that gate resistors.
72mW are the quiescent loss, 336mW is the the TOTAL charging loss which is divided between the driver and other resistors in the chain. So including ALL the 336mW as contributing to the temp rise is incorrect. Am I missing something?
Thank you
Thanks.
I've spent the last week learning about the switching losses from TI's datasheets and I was wonder why it never matched up with my simulations. Thank you for clearing this up!!!!
👍Thanks for sharing.
👍🙏❤
🙏👍😊