Would love to know the history behind Enjoy-Digital , Catherine/Whitequark and AmaranthHDL ! From what I understand, Travis Goodspeed originally commissioned Enjoy-Digital to make LiteX, which is described in Migen... this later became nMigen, but seems this now has a fork to Amaranth HDL... and there seems to be a dispute in the M-Labs and whitequark (former affiliate of M-Labs?) over the direction/brand of nMigen. Also, any thoughts how it compares to Chisel or Spinal HDL? For example isn't VexRiscv for litex written in SpinalHDL? I'd like to do an SoC based design for a Trenz SMF2000 board.. using either LambdaSoc (Amaranth HDL) or LiteX (m-labs or whitequark's Migen/MiSoc). Ideally, I'd like to leverage off-the-shelf IPs (litescope, , ValentyUSB, minerva or VexRiscV). I'm looking at writing a bridge that allows a CPU master to access AHB-Lite and APB3 slaves, all from the Cortex-M3's AHB Fabric-Interface-Controller. (BTW, there's a great blog post on CrowdSupply for Cynthion titled "Moondancer: A Facedancer backend for Cynthion") The debugging tools available for software development have become very sophisticated.. with advanced breakpoint capability, stepping, realt-time variable watching (swv), etc.. with HDLs, it seems the process of debugging hasn't changed and still requires manually writing thousands of test-benches! (Altera's old Max+Plus II Waveform Editor you can could draw your waveforms, then simulate!) Do you know if there's been any development in the area debugging of logic? Everything I've seen still uses test-benches (Icarus Verilog, Verilator/signalflip-js, Aldec Active-HDL, Metrics Cloud Simulator, GHDL for VHDL)!
Great idea guys! It is about time to start developing FPGAs on Open Source. Cannot remember what happened to the Google SoC development but this looks promising. Just a lot of hard works as usual. I hope you have openings for people who would like to join and help. Let us know.
Excellent presentation. I would like to know more about the monitors. For example, I can observe data/traffic going and coming from every master and slave module on the SoC?
Hello, I am amazed with this design concept through python. I wonder if it is foreseen to give support for an analog design flow or will it be limited to digital designs only.
A great presentation. Both comprehensive and comprehensible - a rare combination to achieve. Well done.
Great !
Would love to know the history behind Enjoy-Digital , Catherine/Whitequark and AmaranthHDL !
From what I understand, Travis Goodspeed originally commissioned Enjoy-Digital to make LiteX, which is described in Migen... this later became nMigen, but seems this now has a fork to Amaranth HDL... and there seems to be a dispute in the M-Labs and whitequark (former affiliate of M-Labs?) over the direction/brand of nMigen.
Also, any thoughts how it compares to Chisel or Spinal HDL? For example isn't VexRiscv for litex written in SpinalHDL?
I'd like to do an SoC based design for a Trenz SMF2000 board.. using either LambdaSoc (Amaranth HDL) or LiteX (m-labs or whitequark's Migen/MiSoc). Ideally, I'd like to leverage off-the-shelf IPs (litescope, , ValentyUSB, minerva or VexRiscV).
I'm looking at writing a bridge that allows a CPU master to access AHB-Lite and APB3 slaves, all from the Cortex-M3's AHB Fabric-Interface-Controller.
(BTW, there's a great blog post on CrowdSupply for Cynthion titled "Moondancer: A Facedancer backend for Cynthion")
The debugging tools available for software development have become very sophisticated.. with advanced breakpoint capability, stepping, realt-time variable watching (swv), etc.. with HDLs, it seems the process of debugging hasn't changed and still requires manually writing thousands of test-benches!
(Altera's old Max+Plus II Waveform Editor you can could draw your waveforms, then simulate!)
Do you know if there's been any development in the area debugging of logic? Everything I've seen still uses test-benches (Icarus Verilog, Verilator/signalflip-js, Aldec Active-HDL, Metrics Cloud Simulator, GHDL for VHDL)!
Great idea guys! It is about time to start developing FPGAs on Open Source. Cannot remember what happened to the Google SoC development but this looks promising. Just a lot of hard works as usual. I hope you have openings for people who would like to join and help. Let us know.
Excellent presentation. I would like to know more about the monitors. For example, I can observe data/traffic going and coming from every master and slave module on the SoC?
Hello, I am amazed with this design concept through python. I wonder if it is foreseen to give support for an analog design flow or will it be limited to digital designs only.