Did you try to buy a RTX 50 card and if so, did you get one? It was impossible to get a FE card here in Germany, scalper bots bought the official NVIDIA supply before launch. I think the low stock is most likely due to the limited GDDR7 supply. Currently, only Samsung manufactures these chips.
Nvidia sale site died shortly before it went live, and by the time I got connected it was far too late. I did see AIB stock elsewhere but that went near instantly too.
I tried getting one, saw the prices, and saved myself 5000+ EURO's since I didn't need to buy a completely new system around that 50 series. My 3080 will have to do :P
the joke is AMD changed their numbering system expecting the 5070 class to match around the 4080, pushing price performance up and the 5080 to be priced again around $1,200 not the super. Using GDDR7 gained Nvidia what exactly? Hot air at CES, cold water poured on at review and the RTX 50 is vapour at retail
I agree. I have been learning about nodes, lithography and computer hardware since I was a kid. I learn nothing from the average channel but so much from this one. Incredible information here
For the cost of the silicon you should also mention that the worse yields will end up as RTX5090 while the better yields will be used as B6000 workstation cards which somewhat lowers the cost for the 5090 dies.
5600X3D was a Microcenter exclusive initially. RX570D or RX580D? Where AMD had cut down versions for the Chinese market. nVidia is being forced to only export cut down chips to China. Witnessing how we don't see multiple tiers of cards out of one die on the mass market means the current down binning is enough in most cases such that a "sub RTX 5090" isn't needed. Did the last generation's Ti and Super have old chips binned or new chips?
@ Depends on yields. For the 3090 (95% enabled die) most dies ended up as lower tier 3080 instead (Nvidia wanted to sue Samsung for the poor yields, then they settled with a discount for the manufacturing of that die.). For the 4090 (85% enabled die) only a few were turned into more cut down RTX5000 Ada, basically the 4090 was the lowest tier model on that die.
Fun fact: Nvidia is the largest vendor of RISC-V tech in the world. They have been using this ISA for various purposes (i.e. command and state processor logic) since at least Volta and Turing.
Thank you, no one in the main coverage of the 50 series really mentions the chip yield. Approaching limit of the current node makes me keen on the next generation, maybe we can see another big jump.
@@aetheriality They will likely use the TSMC 2nm node, skipping the 3nm node entirely, as the 2nm node is just a lot better, and I don't think Nvidia wants to leave the door open to AMD being the only one to use a 2nm node for a next gen high-end GPU.
I love the detailed mm^2 breakdown. Do you care about how large nvlink was in Turing and Ampere, just to see how much area was saved when they removed it from Ada or perhaps how it compares to PCIe? Just an idea. No need to do it.
I think the "memory bus size determines chip area" argument is a bit more nuanced in practice, because the exact layout of the memory interface on the die isn't fixed. With a large chip it obviously makes sense to arrange it in a wide and shallow configuration, but that doesn't mean they couldn't have gone for a narrow and deep configuration instead! Arrange the compute first, then place the memory interface like a donut-shaped ring around the compute. The thickness of the donut is determined by its circumference (the total die area for the memory interface is fixed), which in turn is a direct result of the size of the compute part. This would avoid the empty space issue.
True. And it is easy to visualize. Just rotate each 32bit controller by 90°. Same controllers, same layout, same 512bit interface, but you end up with much smaller circumference and thus die size of a chip.
Interesting to see this technical perspective on things like the 5090 max power draw. Mainstream reviewers don’t talk about the why, they just talk about the basic features.
Always happy to see a video from you, and great timing with that one. Despite failing to beat the bots for a 5080 I can at least learn more about Blackwell until more drops are arriving and getting one myself :)
Dass du dir echt die ganze Arbeit machst das zu analysieren und es noch so verstädlich erklären kannst hat meinen Vollen Respekt verdient. Ich freue mich jedes mal wenn ein neues Video raus kommt und ich was neues lernen kann. 🤟💌
Vielen Dank für deinen Kommentar. Ich kann es so gut erklären, weil ich es erst selber mühsam verstehen muss. Und wenn selbst ich es checke, kann es jeder verstehen :D
Nice, logical walkthrough of the chip. Thanks. I have a system on order with a 5090 - can't wait! (won't see it until towards the end of March, but hey..)
Not sure what I was expecting from RTX 5090. On a paper, it looked very impressive, especially that jump in memory bandwidth. But in gaming benchmarks rather disapointing, more performance for more power. Efficiency improvement within the margin of error. AMD ditching high-end products for this gen hints that they were having issues in consumer multi-GCD GPUs. I just want to see Nvidia going into panic mode when they don't have ready answer against AMDs ability to glue chips together.
It’s disappointing in older games but in heavy ray tracing games, it is getting 40-50% uplift over the 4090. Going forward as more games come out, I do believe the 5090 will get a chance to stretch its legs.
It is far from a disappointment. Gamers like to move the goal posts around a lot. Card price goes up and has higher efficiency gamers cry about prices, prices go down but efficiency gains aren't the greatest then gamers cry about that. I'm curious what you think AMD's ability to glue chips together is going to achieve. Do you think it is going to break the laws of physics or something?
@@apersonontheinternet8006 It does not necessarily break physics, but GPU market prices, I hope. The cost per chip is exponentially lower for smaller chips due to more dies per wafer and the higher yield rate. The multi-GCD design gives AMD potential for a few things 1) Focus their design and production into 1-2 GCDs used in all their product tiers 2) undercut Nvidia prices even more 3) perhaps undercut Intel GPUs 4) glue enough GCDs for super-chip that can brute-force above Nvidia xx90 cards. AMD already has multi-GCD products for data centers (High Yield has a video about MI300, go check it out if interested), so it's only a question of time when multi-GCD lands the consumer market.
There was no meaningful manufacturing process node shrink this generation. The 40 and 50 series are on the same process node. People forget the 30-40 series was a such a massive performance jump due to the move from 8nm samsung to 5nm TSMC.
The TU102 die (RTX 2080 Ti) was within touching distance at 754mm². That's >99% the size of GB202. GB202 is certainly the most expensive to manufacture, though. TSMC 12nm was cheap compared to TSMC 4nm - something to the point of a quarter or a fifth the price per wafer.
According to NVIDIA TU102 was 754mm2, while they say 750mm2 for GB202. So that would make Turing larger. But the measured GB202 is 761mm2. Anyways, both chips seem to be pretty close. But Turing was on a inferior node, even for the time.
Can you explain why you think the PHYs couldn't be wider and take up less shoreline? The Radeon 290X is a 512bit card on a 448mm² die. Even being more complex, surely the PHYs could be made wider and take up less space around the die.
I’m sure GDDR7 PHYs are more complex and thus larger than GDDR5 PHYs. But that’s actually a great question! The HD 2900 XT also had a 512-bit bus iirc.
i had the radeon 290 and it was a real beast and fun to play games with. it was better than nvidias cards in every way. they even made models with 6gb vram and i think some 8gb ones too. i had an xfx dd black 290 and that thing was great for 24/7 overclock. ran at 1140mhz gpu and 2650mhz vram. the following r9 390 and 580 series were great too. the radeon 5700xt held up until recently, amd gpus really age like fine wine, unlike nvidia...
Great video thanks!!! I totally agree with your assessment re. the 5090 RAM-bandwidth need for AI. Non-batched token-generation during LLM-inference is mostly limited by memory-bandwidth. Pumping all the many billions of AI-model parameters through the compute-units for each and every token generated (as well as the KV-cache values, etc.) is the bottleneck. E.g. even on modern arm64v8.4 and upwards, the CPU's matrix/vector-compute support alone is able to saturate its 130+GB/s 128-bit LPDDR4X bus (it does not even need any GPU/NPU to saturate it - see llama.cpp Q4_0 GEMM/GEMV acceleration on Snapdragon X). The GB202 has nearly infinitely more compute-power, so having a 2TB/s bus will still be its (very high) token-generation bottleneck. Prompt-processing, training,... is a different story, there its compute-horsepower will shine.
@@mimimimeow Im running even bigger Rajinitek Morpheus II Core edition and since it covers the equally massive TU102 die on my 2080Ti i would assume it also covers the GB202 die.
If I suddenly found that this channel has thousands of videos, I would have to take next week off work to watch them all. Truly a wonderful treat for those that are interested in the subject.
I appreciate the cost estimate you’ve provided for the 5090. At MSRP, they should still make a gross profit of approximately $1000 per unit excluding R&D costs. That being said I’m perplexed why they have reduced supply of this card. Wouldn’t it make sense to average out the r&d costs over larger amounts of units sold? It would be more profitable for them. The R&d cost on the cooler alone is not negligible.
The RnD was funded by and for AI. That is already paid for lol and not by gamers. This is pure 100% profit on these ridiculously overpriced GPUs. (Not MSRP but aibs for $2800 etc)
Plus, there is also probability that they want to ship at least some cards before tariffs will hit. Then, they could claim that they wanted to sell for MSRP, but tariffs would jank those prices even higher.
@@christophermullins7163 you know how I know you’ve never been in charge of anything or have never ran your own business? Really wish you w4 types would stick to w4 things because calling all of your ideas half baked is being very generous.
The video is very good; thank you for your contributions, High Yield. It’s a pity you couldn’t locate the AMP (likely an accelerator/processing module) implemented with a RISC-V, as I assume it must take up very little space and is impossible to find without help from Nvidia’s engineers. There’s one thing I don’t quite understand (forgive my lack of knowledge): When Nvidia disables certain functional units on the die to increase the probability of a die meeting its commercial specifications, is this deactivation analyzed and performed on a per-unit basis, or are the same units always disabled across all manufactured dies? Thank you so much again.
Fantastic analysis, as always! It's interesting to see how much die space is disabled for the sake of yields, as well as the reason behind the bump to a 512-bit memory interface. Considering how tiny the raster units are, I wonder if they could just double the number of them to dramatically increase raster performance in games, or if the raster performance wouldn't scale properly. Just curious.
Always love you die shot videos. I would love to see you take a look at both Arrow Lake and Strix Halo. In my opinion having done a good bit of packaging design myself, this die looks like it is ripe for splitting down the middle in a future MCM design. The crossbar placement right through the exact center of the GPCs and cache is what gives me that feeling when combined wit hthe fact that GB203 appears to basically just be one half of this die layout. Speaking of which, I would love to see some GB203 (5080) die shots in similar resolutions to see if it really is built like that.
Good observation, but let me let you in on a little secret; it basically already is split down the middle. The 90 cards were always 2x the hardware of the 80's, but in the past we ran two separate dies on a single PCB run in SLI. The 90's went away with the GTX 690 because power and heat management was getting out of control with the ever increasing core counts. The 3090 and 4090 were not true 90 cards as they only had roughly 1.3x - 1.6x the hardware, so this is our first true 90 card since about 2012. With the launch of the 50 series I'd say it makes a lot more sense as to why nvidia ended support for SLI. It relieves pressure from 80 cards sales while still providing that SLI-like power to those that need it without all the pitfalls of SLI. I get annoyed with the likes of GN and HU talking about how the 5080 die has been cut or that the big gap between the 5080 and 5090 is just so nvidia can stuff in Supers and Ti's. The 5080 wasn't "cut down", the 3090 and 4090's were the ones that were "cut down" and that was very likely due to heat management concerns. I think nvidias cooler redesign is evidence of this, such a clever yet simple and elegant solution for dealing with all of that power required for these insane core counts.
Awesome! Really makes you wonder why HBM didn't become mainstream. For CPUs, it makes sense that the end customer can choose how much RAM they want to add, but GPUs always come with a fixed memory capacity. I wonder if they could even shrink the die size by switching to HBM vs external chips while largely improving memory performance.
@@nguyenminh7780 Certain components, such as sram for cache, stopped scaling due to limitations in the actual device physics. Others, such as PHYs, are limited by needing to be built up in the metal layers of the chip. Those layers get progressively larger as you get away from the transistor layer. Since the PHYs have to interface with the outside world, they end up limited at least in part by how you intend to connect to them.
Learned a lot in this talk, particularly about the memory interface. I would never pick up one of these just for gaming. This seems like a card for a 3d or ai professional, who is making $$ with their hardware.
Yay!! New video! Btw, ita awsome to see how many more subs you have gotten! I changed my YT name, so im sure you have no idea I am, now, lol. No worries, just happy you are back!
Calling it the biggest Geforce chip ever is slightly disingenuous. Technically correct, yes, but the TU102 (RTX 2080 Ti) at 754mm² is 99.1% of the size. That's just shy of margin of error. GB202 is certainly the most expensive to manufacture, though. TSMC 12nm was cheap compared to TSMC 4nm - something to the point of a quarter or a fifth the price per wafer. edit: Excellent analysis, though. Thank you very much for sharing your thoughts.
This is not a deep-dive, this is only scratching a surface. You can talk about each and every building block of this chip for hours, if not for days. And you know this much better than me :)
Isn't it correct that the raster engine is a separate block from the ROP? I read a white paper from Nvidia about the Blackwell architecture and on the block diagram they are separated from each other
That's correct. Historically ROPs were part of the L2 cache/memory controller. Raster includes culling, ..., and rasterization (making triangles into fragments/pixels before feeding them to the SM for pixel/fragment shading) hardware whereas the ROP is for "render output" at the very end of the process. It stores only pixels/fragments (maybe "primitives" e.g. planes) iirc and is in charge of blending colors and Z. (zrop and crop).
Raster and ROP are separate but very close together. The reason is that the ROP do the z-test to eliminate hidden triangles, hidden faces, and so on. And in some cases, the z-test can be done immediatly after rasterization ! In the absence of transparent textures, for example, or when no shader mess with the z coordinate. And the driver can configure the graphic pipeline to choose either to do the z-test early, or at the end of the pipeline, after analysing the shaders and some other things. So it's better if they are close together in the case of early-test. So separate, but packed together, with a direct connection between the two.
As far as the reviews goes, the integer calculation upgrades this generation doesn't benefit gaming workloads that much, making it sound like a very compute-centric design. What I do find interesting is undervolting results of the 5080 suggesting that this new architecture can hit 2.7+GHz with 0.875V while the last generation requires more voltage to do so. Even more interesting is how, despite the low voltage, these new cards still consume a lot more power core for core when compared to 40 series at a similar voltage, and even if accounting for the extra performance the higher clocks get, the 50 series is less efficient for gaming core for core at the same voltage & much higher clocks. Seems like Blackwell's VF behavior is quite different from Ada, and I'm definitely looking forward to see some efficiency curves
With the massive AI power the 5090 has, I’m surprised Nvidia doesn’t release multiple DLSS models across their stack. The 5090 should be able to run a much higher parameter count model
So, 10.6% cut down GB202 (involving cache, encoders, and computer) and the same process node as the AD102… Either they’re planning a 5090 TI to give all the early 5090 adopters buyers remorse later down the line OR they cut it down to account for the higher power demands of the 5090 and leaving power budget in the standard 1800W budget of the traditional North American 15A outlet. I doubt it’s the latter but I’d love to be surprised.
Having some education in graphics programming but not being a specialist, this is really cool to see. From my perspective, things like the raster engines are part that I only configured. I only have a very rudimentary overview of how they actually function. My typical point of contact would be to configure them for depth testing, i.e. checking if the tested triangle at the specific pixel has a lower depth value than the depth buffer, thereby indicating that the triangle is the closest object to the camera/unobstructed and should therefore be rendered onto the output image. I do know enough about these processes to do some more interesting stuff with it (like abusing the rasteriser for custom alpha masking), but that's about it. It's satisfying how it physically sits in the same position as it does in the logical render pipeline : Between the caches from which all that data will be loaded, and the GCPs that will do the actual shading if the depth test passes.
I saw no mention of the transistor type or thoughts about switching to GAAFET for future NVidia GPUs. Is it realistic that GPUs of this size will switch to GAAFET within the next 1-2 generations?
2:30 Are we really sure about that? AMD Hawaii had a 512-bit GDDR5 PHY with only ~440 mm^2 of area. OK, they likely need more die area to deal with PAM3, but it still feels like an incomplete explanation.
Around 12:00 you mention GB202 is more like a beefed up AD102, this strikes on a nomenclature oddity i noticed very early on - the 200 prefix instead of the usuall 100. Its widely understood that early stage designs are often developed in parrallell before a final design is settled on and proceeded with. Seeing the results, is there any chance that Blackwell is actually an early Ada Lovelace design, perhaps a more accellerator design, that Nvidia went "back" to for current gen due to some limitation or another? This would also add further reason to stay on N5 family, as PDK work was already partially completed. It could signal troubles (in design, manufacturing, yeild, or returns), or simply keeping an ace up the sleeve approach.
It's possible that Blackwell and Ada were developed as sibling architectures. I could see them giving the Blackwell team more time to put things out than Ada to iron out the twin dual-mode ALUs and the AMP setup, as well as waiting on GDDR7. Basically, this is what Ada would look like with more time in the oven. I know that Intel used to do this quite a bit, for example with Raptor Cove and Redwood Cove, where different sub-teams both took Golden Cove and worked towards different ultimate goals (consumer vs server) and targeted different nodes with their designs. Those cores are twins and they look the part in benchmarks, trading wins and losses but with very similar designs from their shared direct predecessor. I would not be surprised to hear that a version of Lion cove with SMT was developed next to the one we got on consumer chips, or that a smaller 6-wide Skymont was also tried.
I feel like this design would make it hard to BIN down defective chips. Maybe that explains the large gap between the the 5090 and the 5080. It looks like gamers are getting the scraps. I have had that feeing that gaming has been low on the concern shelf for some time and that DLSS was more if a "what can we use this stuff for when playing games instead of mining etc". I am cynical when it comes to Nvida after a couple decades of building. I gave them multible chances and every time I regretted it in short order. Usually because of their misleading/"embellished" marketing. Anyway, great breakdown as per usual!
No, the large gap is because this is the first real 90 card since the GTX 690. The rage bait influencers won’t tell you this because they know bad press gets more clicks, but the 90s were always 2x the hardware specs of the 80s. The 3090 and 4090 were the exception likely because nVidia was working out power and heat management which is very obvious with the 5090s new cooler design. 90 cards are literally our replacement for running 2x 80 cards in SLI. Once you start to understand that it all makes more sense, just don’t expect Beave Sturke and the other loser influencers to tell you this because they make a lot of money off of their Intel and nVidia hate watchers. The 3090 and 4090 were cut, the 5080 is not.
sufficient analysis. not sure how accurate this is. no one has them. And chips will be getting much bigger in 20 years hopefully 5 - you may see the manufacturing process change from starting with large circular wafers to starting with a long silicon bar. allowing them to keep etching the bed until an error is detected, then sliceing ze bar at its error terminal. this would allow for a chip to be many inches long. 3in to 12in. imagine having a computational die 10 inches long. you could fit the cpu ram gpu and everything else all on one monolithic die. couple that with etching the water pathways directly through the top bits of the chip and palladium infusion to prevent degredation the power gain would be a moonshot step into the future. And its all possible with the current equipment. I hope this information helps us get us the Artificial Intelligence we Deserve. Changing the ATX standard to an all pcie insertion standard and boom. Now you have a central circuitboard with 5+ pcie slots filled with watercooled GPU, CPU, RAM, NVME, NPU, etc. all communicated directly with one another by pcb trace. There is a lot of improvement to be made in computer science but i fear it is just trickling out so they can squieze every cent from our pockets each year. bye
@ Sure graphene has been promising for the past 20 years but a super material like that wont get made before more advanced AI is born. AI will make that material possible to produce. Theres no need for it yet the current materials are sufficient
Considering the sheer amount of silicon real estate that gets essentially wasted even with a ~11% cut-down, I wouldn't be surprised at all if in about 9-12 months we'll see a GB202 based 384 bit 4080ti 24GB with somewhere around 15.000 CUDA cores for ~$1.500. Just smack in the middle between GB202 and 203. I'd wager they're setting aside dies for something like that already.
if ALU is about 50% of the die, couldn't they go with 3d stack? compute on the top die, and cache, memory controller and I/O on bottom die. I think first AMD will try with this design in their UDNA architecture.
5090 is successor to crown chips of Nvidia enthusiast line for those chips it isn`t the biggest there was TITAN V, titan RTX and what most important GeForce RTX 2080 Ti with bigger/similar chip sizes.
The cache cutdown isn't probably like that. More probable case is that 1/4th of each block. Basically, keeping the GPU standard way of handling cache. There's a crossbar between GPC:s and cache and a direct one to one link to memory controllers and each cache block will cache things that are handled from that memory controller.
This video is real hard to read on a phone, with all that tiny text. It would be helpful to zoom into the parts you're talking about more often. Also, the die yield calc section would really benefit from larger text. I'm sure it looks great on your big 4k monitor, but that doesn't reflect most viewers experience. Yes, I know I can zoom the video, but I shouldn't have to all the time.
Hey great video Can you explain how each part is designed to do a certain task? How some cores multiply matrixes and others do encoding... I dont get how thats a hardware specific thing
GB200 is barely a chiplet design. They have two big backwell GPUs connected to each other in a single die, so technically they are chiplets, even with a giant size, but it doesn't scale (max is two chiplets), or is cheaper to produce, or reduce power draw, or share memory. This is unlike AMD MI300 that has up to 8 much smaller XCD vertically stacked, sharing memory, and can even have a mix of XCD and CCD. For comparison each XCD has 40 CUs, while one Blackwell GPU has 132 SMs. I expect GB200 to cost a lot more than a MI350. There are no real advantages with GB200 interconnected GPUs. Might as well have separate chips. It's a similar architecture to MI250X, two chiplets glued together.
You're wrong, the last card that did that was the GTX 690 which had to be run in SLI that comes with its own efficiency issues. While you are correct that it doesn't scale, it absolutely scales better than SLI which was the entire point of ending support for SLI. People grossly misunderstand what the 90 cards are, they think the 90 cards replaced the 80 cards as the flagship when in reality it is the flagship 80 card in modern "SLI". I think once people do a little research on the old 90 cards and realize what nvidia is doing they will have a greater appreciation for it.
It's great to see a 512-bit memory bus again, last one was 10 years ago on AMD R9 390X. Performs as expected in lattice Boltzmann. And great that it is only 2-slot. But the $2k price tag and 575W TDP are a bummer.
Looks like there is potential for a 5090Ti if they find enough yield on chips with fewer defects. Also can you please do an analysis of Apple’s M4/Pro/Max chips?
I would be interested as to how many Megabytes of bandwidth you think is actually appropriate for games. I can appreciate that PCIe is slow and has very limited bandwidth so you will not properly be able to update things in real-time. But saying that not being able to update memory in real-time because games don't need to is a bit weird.
I’ll admit when I’m in over my head and this is that time. But can I ask with many mixed views and a lot of disappoint with gaming improvement that.. while it does interest me.. I really would like to know as an RTX 4090 FE owner (that the latest Nvidia app updates were amazing! Idk how but War Thunder was using 80-98% GPU without streaming even and now is at like max 12% GPU usage idk what they did fully) But what I can never find online is anyone discussing architecture improvements for creators.. Streaming while gaming … could this help me not need to do a dual computer setup possibly with multiple 4K outputs? I mean are there any major improvements for streaming / and video editing work in adobe premier pro and photoshop / Lightroom .. but mostly anything worthwhile over the 4090 worth trying to change in gains in performance I feel must be there by these massive jumps up to 512 bit and memory speed and amount.. and I heard you mention the band in the middle being for video encode and decode? What I can’t find is anyone discussing or doing real testing with the new architecture (heck even the more controversial 5080s.. I can’t get past memory amount though.. but I will say the ProArt series of the 4080s dual was something I considered! With pro art motherboard and love of the aesthetic with so few good looking professional cards). But .. If you’re working and streaming and doing regular 4K video editing WITH DUAL 4K monitors (soon to be 3x 4K 32”). With a lot just sitting there being used without any work being done…. Like would you expect a large worthwhile increase in professional applications of this card over the 4090? In your opinion? And does anyone know of anyone with better information or resources on it for professional work and or streaming purposes!?
Also any changes ever regarding the fact with dying Intel CPUs (13900k* I have & 14900k) - I’ve always hated that to film in 10ft color that the GPU can’t assist the encoding or whatever to move through timeline and …. In a way I almost want to shoot in lesser quality just to avoid this like like my a6400 can at max vs Sony A7IV 10bit - If ever a GPU could or would allow native support of the 10 bit coded to not put that on the CPU only…. I mean.. that would be A MASSIVE BIT OF NEWS TO SHARE! But I can’t find anyone talking about anything like this…. Are there any upgrades that may allow for a change like that with this generation? Or ever? For native support of 10bit color codec in premiere pro or any program?
Strongly dislike Nvidia's anti-consumer habits, & totally uninterested in anything _GeForce_ in the near term... BUT A HIGH YIELD VIDEO ABOUT THIS... INSTANT WATCH!! 😂
super interesting video - very precisely highlights nvidia's motives for this generation. no thought for the average gaming consumer, but marketed right for them. 32gb gddr7+512bit bus is way too much, and clock are somehow lower because the cores are underpowered. Wonder what they could have done if they had done what you said and focused on raw performance gains rather than just memory/int32 enabled cores. 4090 was memory starved, but I feel like a 28gb gddr7/448 bit running at even 28gbps would have been enough to not throttle the cores, with the addition of being way cheaper and less power draw. Definitely could have been priced around or under the 4090 msrp, but they got overzealous or greedy or both. What a shame. If only nvidia listened to people like you :(
Did you try to buy a RTX 50 card and if so, did you get one?
It was impossible to get a FE card here in Germany, scalper bots bought the official NVIDIA supply before launch. I think the low stock is most likely due to the limited GDDR7 supply. Currently, only Samsung manufactures these chips.
I'm sticking with my 4090 for many more years.
Nvidia sale site died shortly before it went live, and by the time I got connected it was far too late. I did see AIB stock elsewhere but that went near instantly too.
But apparently they also just started producing these cards, so they didn't have time to build up a stockpile for launch.
I tried getting one, saw the prices, and saved myself 5000+ EURO's since I didn't need to buy a completely new system around that 50 series. My 3080 will have to do :P
the joke is AMD changed their numbering system expecting the 5070 class to match around the 4080, pushing price performance up and the 5080 to be priced again around $1,200 not the super.
Using GDDR7 gained Nvidia what exactly?
Hot air at CES, cold water poured on at review and the RTX 50 is vapour at retail
New High Yield video out. Time to stick the kettle on and watch. I wish more tech TH-cam channels were like this.
I agree. I have been learning about nodes, lithography and computer hardware since I was a kid. I learn nothing from the average channel but so much from this one. Incredible information here
Cringe
@Ignisan_66 Yes, because knowledge is bad, what?!?
@@christophermullins7163 Can you recommend some more sources of information?
For the cost of the silicon you should also mention that the worse yields will end up as RTX5090 while the better yields will be used as B6000 workstation cards which somewhat lowers the cost for the 5090 dies.
and worse chips could still go into lower tiered cards (though i am not familiar with this gpu gen)
Lowers, lol
@@raw_000 That usually happens, typically they go into datacenter or region specific cards after a while when they've stockpiled enough chips.
5600X3D was a Microcenter exclusive initially. RX570D or RX580D? Where AMD had cut down versions for the Chinese market.
nVidia is being forced to only export cut down chips to China.
Witnessing how we don't see multiple tiers of cards out of one die on the mass market means the current down binning is enough in most cases such that a "sub RTX 5090" isn't needed. Did the last generation's Ti and Super have old chips binned or new chips?
@ Depends on yields. For the 3090 (95% enabled die) most dies ended up as lower tier 3080 instead (Nvidia wanted to sue Samsung for the poor yields, then they settled with a discount for the manufacturing of that die.). For the 4090 (85% enabled die) only a few were turned into more cut down RTX5000 Ada, basically the 4090 was the lowest tier model on that die.
Fun fact: Nvidia is the largest vendor of RISC-V tech in the world. They have been using this ISA for various purposes (i.e. command and state processor logic) since at least Volta and Turing.
Interesting information, especially since NVIDIA tried to buy arm.
Thank you, no one in the main coverage of the 50 series really mentions the chip yield. Approaching limit of the current node makes me keen on the next generation, maybe we can see another big jump.
6090 HAS to be a big jump
@@aetheriality funny graphics card amirite.
@@aetheriality They will likely use the TSMC 2nm node, skipping the 3nm node entirely, as the 2nm node is just a lot better, and I don't think Nvidia wants to leave the door open to AMD being the only one to use a 2nm node for a next gen high-end GPU.
I love the detailed mm^2 breakdown. Do you care about how large nvlink was in Turing and Ampere, just to see how much area was saved when they removed it from Ada or perhaps how it compares to PCIe? Just an idea. No need to do it.
NVlink is a great idea. It’s actually part of the US restrictions. H800 for example has the same compute as H100, but less NVlink bandwidth.
Hello Linus Blurry webcam capture, I really appreciate what you did out there.
This what quality content looks like. Very impressive 👏🏻
super impressive analysis once again!
Super interesting as always. Thank you !!
0:44 By the available info I could find, the 2080 Ti was their biggest chip so far. (754 vs 744)
Look at the wattage difference.. these dense cores are sucking massive power these days.
@@christophermullins7163 theres lot of them
TPU has updated their GB202 die size to 750mm² now. Still smaller than TU102 but effectively the same.
This video includes scribe lines tho. So thats probably adding a bit
GV100 was even bigger at 815 mm², though not a GeForce.
I haved waited so long to watch your new video, please continue making more videos
A shame it’s not on a new node
Agree. It would have been a much more convincing chip on N3E.
@@HighYieldback to back ~4090 uplifts would have been incredible
also a shame there's no big architectural improvement
I would assume yield rates and price are the reasons it’s not on N3E
@@HighYieldtsmc n3 yield is actually very bad. Don’t trust the media. Yield rate for Apple m4 is less than 50%.
As soon as I saw this channel has new activity, my heart went up in joy. Such an underestimated channel.
Thank you Max, I really appreciate your approach to high-quality content!
I think the "memory bus size determines chip area" argument is a bit more nuanced in practice, because the exact layout of the memory interface on the die isn't fixed. With a large chip it obviously makes sense to arrange it in a wide and shallow configuration, but that doesn't mean they couldn't have gone for a narrow and deep configuration instead! Arrange the compute first, then place the memory interface like a donut-shaped ring around the compute. The thickness of the donut is determined by its circumference (the total die area for the memory interface is fixed), which in turn is a direct result of the size of the compute part. This would avoid the empty space issue.
So why would they not do that
True. And it is easy to visualize. Just rotate each 32bit controller by 90°. Same controllers, same layout, same 512bit interface, but you end up with much smaller circumference and thus die size of a chip.
@@sinnwalker Because they are in a business of delivering 20000+ cuda cores.
No. Chip perimeter connect density is saturating too.
@@musaran2 Nothing which few layers of wires wouldn't fix.
Great stuff, thanks!
Interesting to see this technical perspective on things like the 5090 max power draw. Mainstream reviewers don’t talk about the why, they just talk about the basic features.
Thanks for the discussion of costs and yields. That section was especially valuable and insightful!
Glad you enjoyed it!
Always happy to see a video from you, and great timing with that one. Despite failing to beat the bots for a 5080 I can at least learn more about Blackwell until more drops are arriving and getting one myself :)
Dass du dir echt die ganze Arbeit machst das zu analysieren und es noch so verstädlich erklären kannst hat meinen Vollen Respekt verdient. Ich freue mich jedes mal wenn ein neues Video raus kommt und ich was neues lernen kann. 🤟💌
Vielen Dank für deinen Kommentar. Ich kann es so gut erklären, weil ich es erst selber mühsam verstehen muss. Und wenn selbst ich es checke, kann es jeder verstehen :D
Nice, logical walkthrough of the chip. Thanks. I have a system on order with a 5090 - can't wait! (won't see it until towards the end of March, but hey..)
That was an excellent analysis. I learned a bunch. Thank you.
Not sure what I was expecting from RTX 5090. On a paper, it looked very impressive, especially that jump in memory bandwidth. But in gaming benchmarks rather disapointing, more performance for more power. Efficiency improvement within the margin of error.
AMD ditching high-end products for this gen hints that they were having issues in consumer multi-GCD GPUs. I just want to see Nvidia going into panic mode when they don't have ready answer against AMDs ability to glue chips together.
It’s disappointing in older games but in heavy ray tracing games, it is getting 40-50% uplift over the 4090. Going forward as more games come out, I do believe the 5090 will get a chance to stretch its legs.
It is far from a disappointment. Gamers like to move the goal posts around a lot. Card price goes up and has higher efficiency gamers cry about prices, prices go down but efficiency gains aren't the greatest then gamers cry about that.
I'm curious what you think AMD's ability to glue chips together is going to achieve. Do you think it is going to break the laws of physics or something?
@@apersonontheinternet8006 It does not necessarily break physics, but GPU market prices, I hope. The cost per chip is exponentially lower for smaller chips due to more dies per wafer and the higher yield rate. The multi-GCD design gives AMD potential for a few things 1) Focus their design and production into 1-2 GCDs used in all their product tiers 2) undercut Nvidia prices even more 3) perhaps undercut Intel GPUs 4) glue enough GCDs for super-chip that can brute-force above Nvidia xx90 cards.
AMD already has multi-GCD products for data centers (High Yield has a video about MI300, go check it out if interested), so it's only a question of time when multi-GCD lands the consumer market.
There was no meaningful manufacturing process node shrink this generation. The 40 and 50 series are on the same process node.
People forget the 30-40 series was a such a massive performance jump due to the move from 8nm samsung to 5nm TSMC.
@ I think it’s actually impressive how big the jump is in some games using the same node. The 5080 OC is 5% behind the 4090 with 6,000 less cores.
14:00 Don't forget, the scalper is also making 100% on it...
Titan V had a larger die, but you're right - forgot it wasn't branded GeForce. Still, Nvidia's largest gaming product.
The TU102 die (RTX 2080 Ti) was within touching distance at 754mm². That's >99% the size of GB202.
GB202 is certainly the most expensive to manufacture, though. TSMC 12nm was cheap compared to TSMC 4nm - something to the point of a quarter or a fifth the price per wafer.
According to NVIDIA TU102 was 754mm2, while they say 750mm2 for GB202. So that would make Turing larger. But the measured GB202 is 761mm2. Anyways, both chips seem to be pretty close. But Turing was on a inferior node, even for the time.
@@HighYield Titan V was GV100 though, which was 800+ mm2
@@HighYield Blackwell 2.0 also isn't the best node. Still on 5nm just like Ada and no more efficient. Blackwell should have honestly been 3nm
@@SubhadipSenthat is with HBM memory, chiplet
High quality content, thanks!
Can you explain why you think the PHYs couldn't be wider and take up less shoreline?
The Radeon 290X is a 512bit card on a 448mm² die.
Even being more complex, surely the PHYs could be made wider and take up less space around the die.
I’m sure GDDR7 PHYs are more complex and thus larger than GDDR5 PHYs. But that’s actually a great question! The HD 2900 XT also had a 512-bit bus iirc.
@@HighYieldAnd GTX 280/285
i had the radeon 290 and it was a real beast and fun to play games with.
it was better than nvidias cards in every way.
they even made models with 6gb vram and i think some 8gb ones too.
i had an xfx dd black 290 and that thing was great for 24/7 overclock.
ran at 1140mhz gpu and 2650mhz vram.
the following r9 390 and 580 series were great too.
the radeon 5700xt held up until recently, amd gpus really age like fine wine, unlike nvidia...
Impressive! Thanks, as always. 😸
Great video thanks!!! I totally agree with your assessment re. the 5090 RAM-bandwidth need for AI. Non-batched token-generation during LLM-inference is mostly limited by memory-bandwidth. Pumping all the many billions of AI-model parameters through the compute-units for each and every token generated (as well as the KV-cache values, etc.) is the bottleneck. E.g. even on modern arm64v8.4 and upwards, the CPU's matrix/vector-compute support alone is able to saturate its 130+GB/s 128-bit LPDDR4X bus (it does not even need any GPU/NPU to saturate it - see llama.cpp Q4_0 GEMM/GEMV acceleration on Snapdragon X). The GB202 has nearly infinitely more compute-power, so having a 2TB/s bus will still be its (very high) token-generation bottleneck. Prompt-processing, training,... is a different story, there its compute-horsepower will shine.
Watching this while still rocking my 750mm^2 2080ti
754mm². Same card here.
I'm running the giant Arctic Accelero Xtreme cooler on one and the base literally doesn't cover the entire die 🤣🤣
@@mimimimeow Im running even bigger Rajinitek Morpheus II Core edition and since it covers the equally massive TU102 die on my 2080Ti i would assume it also covers the GB202 die.
Du hast eine beeindruckende Klarheit und Präzision in deinen Erklärungen! Dein Kanal ist wirklich einzigartig. Ich bewundere deinen Geist!
🦝
I see High Yield, I click
If I suddenly found that this channel has thousands of videos, I would have to take next week off work to watch them all. Truly a wonderful treat for those that are interested in the subject.
Love this in depth analysis
Thank you for the very in-depth deep dives as usual! Highly anticipated yields from your channel!
"GB202 is so MASSIVE"
Y know what else is massive
a RTX 4090 die? jk
Definitely not the stock.
Maybe the price tag, yeah.
LOOOOOOOOOOOW
TAPER
FAAAAAAAAAAAADE
the price tag is truly massive
Games are now an AI workload: mega geometry, neural compression, neural radiance cache, and others.
Great video 10/10 - Subbed!
I appreciate the cost estimate you’ve provided for the 5090.
At MSRP, they should still make a gross profit of approximately $1000 per unit excluding R&D costs.
That being said I’m perplexed why they have reduced supply of this card. Wouldn’t it make sense to average out the r&d costs over larger amounts of units sold? It would be more profitable for them. The R&d cost on the cooler alone is not negligible.
The RnD was funded by and for AI. That is already paid for lol and not by gamers. This is pure 100% profit on these ridiculously overpriced GPUs. (Not MSRP but aibs for $2800 etc)
Plus, there is also probability that they want to ship at least some cards before tariffs will hit. Then, they could claim that they wanted to sell for MSRP, but tariffs would jank those prices even higher.
@@christophermullins7163 you know how I know you’ve never been in charge of anything or have never ran your own business? Really wish you w4 types would stick to w4 things because calling all of your ideas half baked is being very generous.
@@apersonontheinternet8006what does w4 mean?
Absolutely incredible insight! Thank you so much for this video! I'm also curious about the idea of underclocking the memory now when I get the 5090.
I wasn't able to get a 5090 so I can't test it myself. Maybe we'll get lucky and one of the usual channels does a test.
@@HighYield I'll try to suggest it in the SFF community where they're always looking for ways to improve efficiency.
The video is very good; thank you for your contributions, High Yield. It’s a pity you couldn’t locate the AMP (likely an accelerator/processing module) implemented with a RISC-V, as I assume it must take up very little space and is impossible to find without help from Nvidia’s engineers. There’s one thing I don’t quite understand (forgive my lack of knowledge): When Nvidia disables certain functional units on the die to increase the probability of a die meeting its commercial specifications, is this deactivation analyzed and performed on a per-unit basis, or are the same units always disabled across all manufactured dies? Thank you so much again.
It happens in the QC stage of manufacturing, every chip is tested individually and sections with defects are identified and disabled.
Fantastic analysis, as always! It's interesting to see how much die space is disabled for the sake of yields, as well as the reason behind the bump to a 512-bit memory interface. Considering how tiny the raster units are, I wonder if they could just double the number of them to dramatically increase raster performance in games, or if the raster performance wouldn't scale properly. Just curious.
Seems the real prize are gonna be the workstation cards this gen. Especially that new 96GB 6000
Спасибо, отличный контент.
Always love you die shot videos. I would love to see you take a look at both Arrow Lake and Strix Halo. In my opinion having done a good bit of packaging design myself, this die looks like it is ripe for splitting down the middle in a future MCM design. The crossbar placement right through the exact center of the GPCs and cache is what gives me that feeling when combined wit hthe fact that GB203 appears to basically just be one half of this die layout. Speaking of which, I would love to see some GB203 (5080) die shots in similar resolutions to see if it really is built like that.
Good observation, but let me let you in on a little secret; it basically already is split down the middle. The 90 cards were always 2x the hardware of the 80's, but in the past we ran two separate dies on a single PCB run in SLI. The 90's went away with the GTX 690 because power and heat management was getting out of control with the ever increasing core counts. The 3090 and 4090 were not true 90 cards as they only had roughly 1.3x - 1.6x the hardware, so this is our first true 90 card since about 2012.
With the launch of the 50 series I'd say it makes a lot more sense as to why nvidia ended support for SLI. It relieves pressure from 80 cards sales while still providing that SLI-like power to those that need it without all the pitfalls of SLI.
I get annoyed with the likes of GN and HU talking about how the 5080 die has been cut or that the big gap between the 5080 and 5090 is just so nvidia can stuff in Supers and Ti's. The 5080 wasn't "cut down", the 3090 and 4090's were the ones that were "cut down" and that was very likely due to heat management concerns. I think nvidias cooler redesign is evidence of this, such a clever yet simple and elegant solution for dealing with all of that power required for these insane core counts.
Awesome! Really makes you wonder why HBM didn't become mainstream. For CPUs, it makes sense that the end customer can choose how much RAM they want to add, but GPUs always come with a fixed memory capacity. I wonder if they could even shrink the die size by switching to HBM vs external chips while largely improving memory performance.
Yield issues coupled with degradation over time at sustained high temps, and prohibitively expensive.
Can you please do a video explaining why some components like the GDDR phys connections on GPUs don't shrink with node shrinks ?
That's an absolutely good idea.
Would be good if he includes why cache memory and video engines also suffer from the same problem
GDDR phys connections are metal, not transistors, and it' mostly transistors that are reduced in size with node shrinks.
@@pedro.alcatra oh ye those and pcie connections too, they don’t shrink that much
@@nguyenminh7780 Certain components, such as sram for cache, stopped scaling due to limitations in the actual device physics. Others, such as PHYs, are limited by needing to be built up in the metal layers of the chip. Those layers get progressively larger as you get away from the transistor layer. Since the PHYs have to interface with the outside world, they end up limited at least in part by how you intend to connect to them.
Great analysis.
Those area % breakdowns shows that there's a large future opportunity for 3D stacking a compute die on top and an I/O + cache die.
Absolutely amazing deep dive! It is incredible to see how massive gb202 really is.
very good video!!
Learned a lot in this talk, particularly about the memory interface. I would never pick up one of these just for gaming. This seems like a card for a 3d or ai professional, who is making $$ with their hardware.
Good stuff, thanks
Yay!! New video! Btw, ita awsome to see how many more subs you have gotten! I changed my YT name, so im sure you have no idea I am, now, lol. No worries, just happy you are back!
Calling it the biggest Geforce chip ever is slightly disingenuous. Technically correct, yes, but the TU102 (RTX 2080 Ti) at 754mm² is 99.1% of the size. That's just shy of margin of error.
GB202 is certainly the most expensive to manufacture, though. TSMC 12nm was cheap compared to TSMC 4nm - something to the point of a quarter or a fifth the price per wafer.
edit: Excellent analysis, though. Thank you very much for sharing your thoughts.
According to NVIDIA TU102 is even slightly bigger as you stated. But this measurement is pretty precise at 761. Plus, it’s on a competitive node.
Amazing work. I’m excited to see what the smaller chip on the 5080 looks like.
I've posted a quick GB203 analysis on X → x.com/highyieldYT/status/1884656106972053926
This is not a deep-dive, this is only scratching a surface. You can talk about each and every building block of this chip for hours, if not for days. And you know this much better than me :)
2:10 I dare you to say "Shoreline" 3 times fast!
I kid... Excellent analysis!
Isn't it correct that the raster engine is a separate block from the ROP? I read a white paper from Nvidia about the Blackwell architecture and on the block diagram they are separated from each other
The Raster Engines have two blocks with ROPs. That’s how I understood it. I might be wrong. Let’s check again.
That's correct. Historically ROPs were part of the L2 cache/memory controller. Raster includes culling, ..., and rasterization (making triangles into fragments/pixels before feeding them to the SM for pixel/fragment shading) hardware whereas the ROP is for "render output" at the very end of the process. It stores only pixels/fragments (maybe "primitives" e.g. planes) iirc and is in charge of blending colors and Z. (zrop and crop).
Raster and ROP are separate but very close together. The reason is that the ROP do the z-test to eliminate hidden triangles, hidden faces, and so on. And in some cases, the z-test can be done immediatly after rasterization ! In the absence of transparent textures, for example, or when no shader mess with the z coordinate. And the driver can configure the graphic pipeline to choose either to do the z-test early, or at the end of the pipeline, after analysing the shaders and some other things. So it's better if they are close together in the case of early-test. So separate, but packed together, with a direct connection between the two.
@guyg.8529 thank you so much for detailed explanation
As far as the reviews goes, the integer calculation upgrades this generation doesn't benefit gaming workloads that much, making it sound like a very compute-centric design.
What I do find interesting is undervolting results of the 5080 suggesting that this new architecture can hit 2.7+GHz with 0.875V while the last generation requires more voltage to do so. Even more interesting is how, despite the low voltage, these new cards still consume a lot more power core for core when compared to 40 series at a similar voltage, and even if accounting for the extra performance the higher clocks get, the 50 series is less efficient for gaming core for core at the same voltage & much higher clocks.
Seems like Blackwell's VF behavior is quite different from Ada, and I'm definitely looking forward to see some efficiency curves
With the massive AI power the 5090 has, I’m surprised Nvidia doesn’t release multiple DLSS models across their stack. The 5090 should be able to run a much higher parameter count model
So, 10.6% cut down GB202 (involving cache, encoders, and computer) and the same process node as the AD102…
Either they’re planning a 5090 TI to give all the early 5090 adopters buyers remorse later down the line OR they cut it down to account for the higher power demands of the 5090 and leaving power budget in the standard 1800W budget of the traditional North American 15A outlet. I doubt it’s the latter but I’d love to be surprised.
Having some education in graphics programming but not being a specialist, this is really cool to see.
From my perspective, things like the raster engines are part that I only configured. I only have a very rudimentary overview of how they actually function. My typical point of contact would be to configure them for depth testing, i.e. checking if the tested triangle at the specific pixel has a lower depth value than the depth buffer, thereby indicating that the triangle is the closest object to the camera/unobstructed and should therefore be rendered onto the output image.
I do know enough about these processes to do some more interesting stuff with it (like abusing the rasteriser for custom alpha masking), but that's about it.
It's satisfying how it physically sits in the same position as it does in the logical render pipeline : Between the caches from which all that data will be loaded, and the GCPs that will do the actual shading if the depth test passes.
I saw no mention of the transistor type or thoughts about switching to GAAFET for future NVidia GPUs. Is it realistic that GPUs of this size will switch to GAAFET within the next 1-2 generations?
TSMC doesn't have any GAAFET in production yet. N2 is meant to switch to it.
Probably 6 years or 3 gems.
2:30 Are we really sure about that? AMD Hawaii had a 512-bit GDDR5 PHY with only ~440 mm^2 of area. OK, they likely need more die area to deal with PAM3, but it still feels like an incomplete explanation.
great video
Around 12:00 you mention GB202 is more like a beefed up AD102, this strikes on a nomenclature oddity i noticed very early on - the 200 prefix instead of the usuall 100. Its widely understood that early stage designs are often developed in parrallell before a final design is settled on and proceeded with. Seeing the results, is there any chance that Blackwell is actually an early Ada Lovelace design, perhaps a more accellerator design, that Nvidia went "back" to for current gen due to some limitation or another?
This would also add further reason to stay on N5 family, as PDK work was already partially completed. It could signal troubles (in design, manufacturing, yeild, or returns), or simply keeping an ace up the sleeve approach.
It's possible that Blackwell and Ada were developed as sibling architectures. I could see them giving the Blackwell team more time to put things out than Ada to iron out the twin dual-mode ALUs and the AMP setup, as well as waiting on GDDR7. Basically, this is what Ada would look like with more time in the oven.
I know that Intel used to do this quite a bit, for example with Raptor Cove and Redwood Cove, where different sub-teams both took Golden Cove and worked towards different ultimate goals (consumer vs server) and targeted different nodes with their designs. Those cores are twins and they look the part in benchmarks, trading wins and losses but with very similar designs from their shared direct predecessor. I would not be surprised to hear that a version of Lion cove with SMT was developed next to the one we got on consumer chips, or that a smaller 6-wide Skymont was also tried.
B100 is used for datacenter; B20x is used for consumer GPUs.
good video, thank you :)
I feel like this design would make it hard to BIN down defective chips. Maybe that explains the large gap between the the 5090 and the 5080. It looks like gamers are getting the scraps. I have had that feeing that gaming has been low on the concern shelf for some time and that DLSS was more if a "what can we use this stuff for when playing games instead of mining etc". I am cynical when it comes to Nvida after a couple decades of building. I gave them multible chances and every time I regretted it in short order. Usually because of their misleading/"embellished" marketing.
Anyway, great breakdown as per usual!
No, the large gap is because this is the first real 90 card since the GTX 690. The rage bait influencers won’t tell you this because they know bad press gets more clicks, but the 90s were always 2x the hardware specs of the 80s. The 3090 and 4090 were the exception likely because nVidia was working out power and heat management which is very obvious with the 5090s new cooler design.
90 cards are literally our replacement for running 2x 80 cards in SLI. Once you start to understand that it all makes more sense, just don’t expect Beave Sturke and the other loser influencers to tell you this because they make a lot of money off of their Intel and nVidia hate watchers. The 3090 and 4090 were cut, the 5080 is not.
love your stuff, would looove to see a deep dive into amds new strix halo apus
Strix Halo will come for sure 👍
@ thank you! Please take your time, your videos are a gift, not an obligation.
sufficient analysis. not sure how accurate this is. no one has them. And chips will be getting much bigger in 20 years hopefully 5 - you may see the manufacturing process change from starting with large circular wafers to starting with a long silicon bar. allowing them to keep etching the bed until an error is detected, then sliceing ze bar at its error terminal. this would allow for a chip to be many inches long. 3in to 12in. imagine having a computational die 10 inches long. you could fit the cpu ram gpu and everything else all on one monolithic die. couple that with etching the water pathways directly through the top bits of the chip and palladium infusion to prevent degredation the power gain would be a moonshot step into the future. And its all possible with the current equipment. I hope this information helps us get us the Artificial Intelligence we Deserve. Changing the ATX standard to an all pcie insertion standard and boom. Now you have a central circuitboard with 5+ pcie slots filled with watercooled GPU, CPU, RAM, NVME, NPU, etc. all communicated directly with one another by pcb trace. There is a lot of improvement to be made in computer science but i fear it is just trickling out so they can squieze every cent from our pockets each year. bye
I don't think we will see sweeping changes to standards like that until we move on to graphene.
@ Sure graphene has been promising for the past 20 years but a super material like that wont get made before more advanced AI is born. AI will make that material possible to produce. Theres no need for it yet the current materials are sufficient
Considering the sheer amount of silicon real estate that gets essentially wasted even with a ~11% cut-down, I wouldn't be surprised at all if in about 9-12 months we'll see a GB202 based 384 bit 4080ti 24GB with somewhere around 15.000 CUDA cores for ~$1.500. Just smack in the middle between GB202 and 203. I'd wager they're setting aside dies for something like that already.
6:55 *NOW is it GPC or GCP?* I think you switched things up...🤯
if ALU is about 50% of the die, couldn't they go with 3d stack?
compute on the top die, and cache, memory controller and I/O on bottom die.
I think first AMD will try with this design in their UDNA architecture.
I am excited by Nvidia's Project Digits and the GB10 based "super-mini" desktop, they say is coming in May for around $3,000US
Excellent, thank you!
5090 is successor to crown chips of Nvidia enthusiast line for those chips it isn`t the biggest there was TITAN V, titan RTX and what most important GeForce RTX 2080 Ti with bigger/similar chip sizes.
The cache cutdown isn't probably like that. More probable case is that 1/4th of each block. Basically, keeping the GPU standard way of handling cache. There's a crossbar between GPC:s and cache and a direct one to one link to memory controllers and each cache block will cache things that are handled from that memory controller.
This video is real hard to read on a phone, with all that tiny text. It would be helpful to zoom into the parts you're talking about more often. Also, the die yield calc section would really benefit from larger text. I'm sure it looks great on your big 4k monitor, but that doesn't reflect most viewers experience.
Yes, I know I can zoom the video, but I shouldn't have to all the time.
Why would the die size be set in stone? A rectangle can have any circumference above (√ area)*4
chips out for Highyielde!
very enlightening video. thanks a lot. .. can the "raster engine" be understood as the equivalent to a shader array in amd GPUs?
Hey great video
Can you explain how each part is designed to do a certain task? How some cores multiply matrixes and others do encoding... I dont get how thats a hardware specific thing
Now I get to get a deep dive in general of a GPU kind that makes use the olden 512 bit memory bus packed as a modern and recent reference
GB202 is 750 mm² vs TU102 - 754 mm². Aka it's not the biggest. + We had GV100 on Titan V with size of 815 mm².
this @high yield
GB200 is barely a chiplet design. They have two big backwell GPUs connected to each other in a single die, so technically they are chiplets, even with a giant size, but it doesn't scale (max is two chiplets), or is cheaper to produce, or reduce power draw, or share memory. This is unlike AMD MI300 that has up to 8 much smaller XCD vertically stacked, sharing memory, and can even have a mix of XCD and CCD. For comparison each XCD has 40 CUs, while one Blackwell GPU has 132 SMs. I expect GB200 to cost a lot more than a MI350. There are no real advantages with GB200 interconnected GPUs. Might as well have separate chips. It's a similar architecture to MI250X, two chiplets glued together.
You're wrong, the last card that did that was the GTX 690 which had to be run in SLI that comes with its own efficiency issues. While you are correct that it doesn't scale, it absolutely scales better than SLI which was the entire point of ending support for SLI.
People grossly misunderstand what the 90 cards are, they think the 90 cards replaced the 80 cards as the flagship when in reality it is the flagship 80 card in modern "SLI". I think once people do a little research on the old 90 cards and realize what nvidia is doing they will have a greater appreciation for it.
You did not show us the power pins and power bus on the die 😢
Its obvious that nvidia use same node because ada and blackwell are developed during same timeline. Blackwell in beginning was ai data centre use.
It's great to see a 512-bit memory bus again, last one was 10 years ago on AMD R9 390X. Performs as expected in lattice Boltzmann. And great that it is only 2-slot.
But the $2k price tag and 575W TDP are a bummer.
I think 2-slot was a mistake. Sure, it's an extremely impressive cooler but if they just kept it 3-slot it could have been so much quieter.
The HD 2900 XT also had a 512-bit bus iirc. A long time ago.
Well RTX 5090 is a server-grade chip at its core, no? What's their pro segment marketed counterpart?
Looks like there is potential for a 5090Ti if they find enough yield on chips with fewer defects.
Also can you please do an analysis of Apple’s M4/Pro/Max chips?
I would be interested as to how many Megabytes of bandwidth you think is actually appropriate for games.
I can appreciate that PCIe is slow and has very limited bandwidth so you will not properly be able to update things in real-time. But saying that not being able to update memory in real-time because games don't need to is a bit weird.
How are these images made? my best guess is X-ray but idk if its this precise. Just curious
I’ll admit when I’m in over my head and this is that time. But can I ask with many mixed views and a lot of disappoint with gaming improvement that.. while it does interest me.. I really would like to know as an RTX 4090 FE owner (that the latest Nvidia app updates were amazing! Idk how but War Thunder was using 80-98% GPU without streaming even and now is at like max 12% GPU usage idk what they did fully)
But what I can never find online is anyone discussing architecture improvements for creators.. Streaming while gaming … could this help me not need to do a dual computer setup possibly with multiple 4K outputs? I mean are there any major improvements for streaming / and video editing work in adobe premier pro and photoshop / Lightroom .. but mostly anything worthwhile over the 4090 worth trying to change in gains in performance I feel must be there by these massive jumps up to 512 bit and memory speed and amount.. and I heard you mention the band in the middle being for video encode and decode? What I can’t find is anyone discussing or doing real testing with the new architecture (heck even the more controversial 5080s.. I can’t get past memory amount though.. but I will say the ProArt series of the 4080s dual was something I considered! With pro art motherboard and love of the aesthetic with so few good looking professional cards). But .. If you’re working and streaming and doing regular 4K video editing WITH DUAL 4K monitors (soon to be 3x 4K 32”). With a lot just sitting there being used without any work being done…. Like would you expect a large worthwhile increase in professional applications of this card over the 4090? In your opinion?
And does anyone know of anyone with better information or resources on it for professional work and or streaming purposes!?
Also any changes ever regarding the fact with dying Intel CPUs (13900k* I have & 14900k) - I’ve always hated that to film in 10ft color that the GPU can’t assist the encoding or whatever to move through timeline and …. In a way I almost want to shoot in lesser quality just to avoid this like like my a6400 can at max vs Sony A7IV 10bit - If ever a GPU could or would allow native support of the 10 bit coded to not put that on the CPU only…. I mean.. that would be A MASSIVE BIT OF NEWS TO SHARE! But I can’t find anyone talking about anything like this…. Are there any upgrades that may allow for a change like that with this generation? Or ever? For native support of 10bit color codec in premiere pro or any program?
Strongly dislike Nvidia's anti-consumer habits, & totally uninterested in anything _GeForce_ in the near term...
BUT A HIGH YIELD VIDEO ABOUT THIS... INSTANT WATCH!! 😂
Why does the video decoding area look so big? Isn't decoding supposed to be a lot easier than encoding?
super interesting video - very precisely highlights nvidia's motives for this generation. no thought for the average gaming consumer, but marketed right for them. 32gb gddr7+512bit bus is way too much, and clock are somehow lower because the cores are underpowered. Wonder what they could have done if they had done what you said and focused on raw performance gains rather than just memory/int32 enabled cores. 4090 was memory starved, but I feel like a 28gb gddr7/448 bit running at even 28gbps would have been enough to not throttle the cores, with the addition of being way cheaper and less power draw. Definitely could have been priced around or under the 4090 msrp, but they got overzealous or greedy or both. What a shame. If only nvidia listened to people like you :(
Insane that normal people can just buy these special rocks inscribed with invisible magic runes
haven't bought a new card in over 10 years, currently on a 3090 from ebay for 1000€ and not planning on switching any time soon
when will they begin to layer all the non-compute on top of the rest... and maybe below it too
I don't care what anyone says this is earth-shattering
Gamers went from being consumers to prosumers.
People forget about the old 90 cards, last true one we had was the GTX 690.
But yes, most gamers need to forget that the 5090 exists.