verilog code for SR FLIP FLOP with testbench

[@shivanshusoni197]

Very useful information for VLSI domain ..... Keep it up bro 🙂❤

[@anandrajofficial1]

Thank u

[@ajitrajkidesfamily1538]

Thanks sir jii

[@deepakkumaryadav6009]

Sir register or counter ka v videos upload Kar do

[@anandrajofficial1]

Ok this weekend, i will try to make.

[@deepakkumaryadav6009]

@@anandrajofficial1 thick hai sir

[@saikishore3380]

It's shows one error bro help me to get clear.... I will post what error it is :
design.sv:13:error:reg qb; cannot be driven by primitives or continuous assignment

[@anandrajofficial1]

are u using system verilog??

[@saikishore3380]

@@anandrajofficial1 EDA play ground system verilog

[@saikishore3380]

@@anandrajofficial1 I need urgent help

[@saikishore3380]

@@anandrajofficial1 contact pls bro it's shows only one error help me to clear what I need to change

[@anandrajofficial1]

@@saikishore3380 edaplayground.com/x/DpQ_

[@rationalthinker9612]

Terrible way to present information. You can barely see your code, YOU NEED TO MAKE IT BIGGER

[@saranshgautam6551]

Choosing Beggar