Sir....kya baat h...in.this DP aapne bina break liye 2 vedio upload kiya h....thnx bhaiya.....aeisa hi karte rahna....n both CN and COA both VVI topic complt karwaoge for sure....I know again ...mata rani aapke evry wish puri Karen....
sir your way of teaching is very nice, i completed CN playlist, now i entered into cao and i am watching 40th viedo, very nice sir , thank you from my side
Thanku sir ♥️ Two days bache hai mere exam ke aap ka lecture dekh kar maja aa gaya Aayesa har collage me teacher hota to..... So beautiful so alegate just looking like a wow 🎉❤
Sir thank you i dont express your favour in words.❤❤❤❤❤ But sir 1 request please delay little bit (video,channel logo) which pop up at last of video i.e. to take screenshot of board
how can the 2 bits of the block offset represent 4 words ? it would be 00 01 10 or 11 the highest is 11 which makes to 3rd word ? i dont get it that how will i be able to tell that which particular word is in the cache like we did in the direct mapping
k-way set associative mapping divides the cache memory into sets, each containing k lines, based on the specified value of k. If k exceeds the total number of cache lines, the entire cache behaves like a fully associative cache, where all lines belong to a single set, effectively reducing the number of sets to 1
In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are placed in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards. The main memory block numbered j must be mapped to any one of the cache lines from. A (j mod v) * k to (j mod v) * k + (k-1) B (j mod v) to (j mod v) + (k-1) C (j mod k) to (j mod k) + (v-1) D (j mod k) * v to (j mod k) * v + (v-1)
Sir agar cache memory ka size 256 words(8 word each)and 2 way set associative then kya no of sets 2 hoga? Kyuki k mod n formula se 0 aur 1 ke elave aur kuch nayi aaya..
"Set-associative mapping allows that each word that is present in the cache can have two or more words in the main memory for the same index address" - can someone please explain me this statement with reference to this video?
Sir I have one question: Consider a system with 4 way associative cache of 256 kb. The cache line is 8 words (32 bits per word). The smallest addressable unit is a byte and memory bits are 64 bit long. a) How many bits are used for tag and index field of cache mapping? b) What memory address can make to set 289 of the cache?
I may forget my home address, but will never forget that Block Size = Line Size :)
😂😂
Exactly
🤣🤣
😂😂😂👍
🤣🤣🤣
Sir....kya baat h...in.this DP aapne bina break liye 2 vedio upload kiya h....thnx bhaiya.....aeisa hi karte rahna....n both CN and COA both VVI topic complt karwaoge for sure....I know again ...mata rani aapke evry wish puri Karen....
one day I will owe my graduation degree to you sir...
😛
I am an M.Tech student in BITS, our professors don't explain this good. Thank you so much Sir!
You are most welcome
Even in Mtech all these subjects are there? And what about the syllabus? Suppose you are studying CO Archi... Is the syllabus same as Btech??
@@sheldoncooper3373 Advanced Architecture is there..
sir your way of teaching is very nice, i completed CN playlist, now i entered into cao and i am watching 40th viedo, very nice sir
, thank you from my side
Never find such a great teacher online.... Thanku sir..
You are like saving life of students😌🙏
NUML Students attendance lgaway
sir aap kisi bhi chij ko easy kar dete hai kitna bhi difficult ho chutkiyo me easy karte hai nice sir
I m very happy coz of u.... mostly I crame these topics bt u make it easy 4 us.... Thnx alot sir 😍💞💞
sir, aap nai rehte toh engineering students kya karte, kyahi pata😅. Thank you so much sir!
What an explanation.
Amazing.
Gajab explanation 💥🔥💥
Thanku so much 🙏u r blessing for us .. may god bless u sir wd all happiness
Dhanyabaad sir... You helped a lot... I bow down to you
Thank you Sir!
I was able to understand this topic only because of you!
Thank you varun sir this video
Thanks a lot sir...you are the best teacher on youtube
Thanku sir ♥️
Two days bache hai mere exam ke aap ka lecture dekh kar maja aa gaya
Aayesa har collage me teacher hota to.....
So beautiful so alegate just looking like a wow
🎉❤
Sir agar aap aise hi padhaoge toh hr paper ki cutoff high jaya kregi. Isse best explaination hau hi nahi sakta...thanks
Sir,I have no words of gratitude for Ur great work 🇮🇳
💞💞💞💞Awesome 🌹🇮🇳🇮🇳🇮🇳🇮🇳
Thnku so much sir ap complex concepts ko easy banatay ho. Mko apka 100%smg aata hai
Thanks from Lahore, Pakistan by a BSCs student
i can't understand a single concept in class ..thank you so much sir your videos very helpful for me
best teacher in the world
Thank you Sir, You way of teaching in deep is so nice.
Your videos have made this subject finally understandable to me . Thank you !
R u cse student??
awesome explanation
Gurujee shandar jabardast zindabaad
Thank you sir I was waiting for set associative mapping!
Great explanation and great energy sir.
kya explain karte ho sir , naman hai aapko🙏🙏🙏
Thank you bhaiya for this video🙏
Very good explanation,sir
Thank you so muchhhhh sirrr
Forever grateful to you❤
Thank you so much for these wonderful lectures🌸
Simple to listen , easy to learn and get a way to implement👍
Thank you so much for clearing my doubt sir! Very well explained!!🤍
Very nice 😊
Sir you explain everything very well thank u sir ...very clear concept ...
The way of teaching is fab ❤️❤️❤️❤️❤️❤️❤️❤️
Thank You so much Sir 😊👌
You are great sir
I was following your tutorials and get A grade in computer architecture
Wow.. Great
@@GateSmashers you are great sir
Sir take love from 🇧🇩
Well explained sir
Very easy explanation
Thank you sir... keep it continue .. eagerly waiting for control unit design topic
Hats of uhh sir😊
It works! Thanks a lot.
Simple ... and great . thanks
Thank you so much Sir, You are really awesome teacher
Great teacher i really appreciate u thanks a lot sir ji god bless u
Tq so much sir you are a life saver ❤️❤️
Sirji !! Aap bahot great kaam kar rhe hooo. Keep it up and jo subject ki videos avi baki hee vo bhi jaldi se daal do plz 😅🙏
Thanks sir ...
I swear i solved all gate problem on direct mapping just after watching ur vedios without picking pen.
sir u r great from pakistan
Thank you sir ji 🙏
Thank you so much brother. Hats off.
Nice, keep on doing Sir
U made dis topic very easy for us. Thank u Sir!
I must watch for processor designer & verification engineers
Thanks😍
thank you sir💕💕
thankú sir ❤
5 minutes engineering channel more easy explanation, no confusion
Thanks bhai jann
Thanks sir g 👍
Thanks man !
Thank u so much
Thankyou sir kal mera paper tha ap se bht acha parhaya hai lekin humen phir bhi nahi aya
Sir thank you i dont express your favour in words.❤❤❤❤❤
But sir 1 request please delay little bit (video,channel logo) which pop up at last of video i.e. to take screenshot of board
nice explanation
Thank u sir
how can the 2 bits of the block offset represent 4 words ? it would be 00 01 10 or 11 the highest is 11 which makes to 3rd word ? i dont get it that how will i be able to tell that which particular word is in the cache like we did in the direct mapping
The highest bit is 16 see vedio one more time he was talking about even bit or odd bit 16 will in set 1 and even 16, in set 2
Will the set no. vary if its 4 way set associative in physical address?
In K-way Set Associative mapping, can the value of K > number of lines?
k-way set associative mapping divides the cache memory into sets, each containing k lines, based on the specified value of k. If k exceeds the total number of cache lines, the entire cache behaves like a fully associative cache, where all lines belong to a single set, effectively reducing the number of sets to 1
😊😊😊😊😊😊😊😊😊😊
Thanks sir
At a given time in each line maximum 4 blocks can be residing right?? or only one block...pl. clarify...
Thanku sir
Tnkx
sir so there is no case of miss in this k-way associative mapping
For ugc exam ur lecture enough?
With same concept their were many isro cse question in past .
In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are placed in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards. The main memory block numbered j must be mapped to any one of the cache lines from.
A
(j mod v) * k to (j mod v) * k + (k-1)
B
(j mod v) to (j mod v) + (k-1)
C
(j mod k) to (j mod k) + (v-1)
D
(j mod k) * v to (j mod k) * v + (v-1)
@@pruthvirajhawale6371 option A
Sir es par examples, numerical s karwa dijiye,concept tough lag Raha hai.
Who is watching in may last 2021🖤
Sir agar cache memory ka size 256 words(8 word each)and 2 way set associative then kya no of sets 2 hoga? Kyuki k mod n formula se 0 aur 1 ke elave aur kuch nayi aaya..
Nahi number of sets 16 hoga
hello ! sir, i have one question what if k =4 or 8
I shall never forget memory is byte/word addressable
how i make the notes of these videos
Sir how can we calculate the tag directory size???
Number of tag bits × number of lines
It's true that he teaches really well. But we never use these subjects in the real world. CN DBMS is ok.
"Set-associative mapping allows that each word that is present in the cache can have two or more words in the main memory for the same index address" - can someone please explain me this statement with reference to this video?
Sir I have one question:
Consider a system with 4 way associative cache of 256 kb. The cache line is 8 words (32 bits per word). The smallest addressable unit is a byte and memory bits are 64 bit long.
a) How many bits are used for tag and index field of cache mapping?
b) What memory address can make to set 289 of the cache?
What is the size of address? If 32 bits then tag field is of 16 bits. If 64 bits the tag field is of 48 bits.
Aap sabhi topic ki video nahi upload karte ho
Sir you don't provide us notes of these topics. So kindly provide us. 🙏🏼
Kaash hamaare zamaane me hote aap aur jab youtube common hota in 2006
6:10
Note:
Sir are you single