Z80 Retro #8 - PCB Design
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- เผยแพร่เมื่อ 27 พ.ย. 2024
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This is part of a TH-cam playlist/series: • Z80 Retro
The KiCad files for this board are here: github.com/joh...
Hackaday project blog: hackaday.io/pr...
This is a discussion of the how & why I did what I did when I routed the Z80 Retro! project PCB board.
Links to the EEVblog videos mentioned are:
EEVblog 1085 - Bypass Capacitors Visualised: • EEVblog #1085 - Bypass...
EEVblog 1176 - 2 Layer vs 4 Layer PCB EMC TESTED: • EEVblog #1176 - 2 Laye...
Music used in this video (Vibe Tracks, Alternate) was downloaded from the TH-cam Audio Library: www.youtube.co...
#Z80
#CPM
#homebrew
#retrocomputer
Hi John, I always learn bits from your videos. Brilliant way of teaching
Thanks!
I have to ditto the comment @MartenElectric. Not only that, they are damn entertaining - I love your humor. I hope you never tire of doing these videos. After almost a year of of gathering parts, I ordered the boards using PcbWay - $57 for 5 of both boards and shipping. BTW, Mouser has 10MHz CTC & SIO DIP chips ( I seem to remember somewhere you saying you could not get the 10 MHz version of one of these chips. (Just in case you do not know this already.)
Time to order some PCBs. Love this project! Thanks!
One last comment, if you go into Preferences under 3D Viewer/General there is a checkbox for Show board body. Uncheck that box and return to 3d Viewer. Rotate the board so that you are viewing it edge on. Zoom in and you can actually see the vias inside the board.
First off, your board is going to be ok as it is because all your parts are very slow.
But you actually only have a good return path for signals on the front side. They couple to the L2 gnd.
Your back layer tracks will have to hunt for a return path and will choose path of least impedance. They might use your L3 5V plane and then run through one of the decouplers, or they might find a GND connected through hole.
Either way it's unlikely to be the smallest loop area.
I only wanted to point that out because people designing faster boards need to understand that or they won't work well/at all/will radiate like crazy.
Also the L1 and L4 GND floods are not a good idea unless you have a very good use case. Don't do it as a matter of course. It does not generally fix any radiation issues.
Don't take my word for it. Watch Rick Hartley's videos.
Filling L1 and L4 is something I used to do after a board house asked for it (or dots) as thieving. I also think it looks nicer. Any down sides?
I've seen Rick's talk on power & ground planes. It is good stuff.... and yes, I ignored one of his lessons. :-|
As you note, with slower signals, we can get away with a lot. As it is, I think it is WAY better than a 2-layer board a'la 1980! In the end, putting the signals inside w/ground on L1 and L4 would be better... but when prototyping & debugging a 10MHZ board, it is nice to be able to cut a trace if/when necessary.
Hi John,
I would always leave undlooded. If the board house needs copper adding for balancing L1 L4 material density they will ask to add some. With modern PCB manufacturing it's highly unlikely.
There is no need to sandwich the signals in the board ... it works just as well with the signals on the outside.
For high speed stuff (by which I mean things with very fast rising and falling edges) you just need the signal traces to be as close as possible to GND.
For your board I would have had L2 and L3 as GND and then I would have routed 5V point to point like a (fat) signal. Then finally I would have scattered some GND vias around so that signals crossing L1-L4 have a parallel return path from L3 to L2 GND.
One trick is to run the 5V as a trace around the perimeter of L3 to distribute around the board, then you can just tap off and do your horizontal and vertical routing to the power pin as normal.
Love the videos by the way, thanks!
When I'm designing a pcb I'll spend literal hours just staring at my design, moving the board around somewhat randomly, looking at where things are routed, looking for better routing options, or even better parts placement.
By the time I finish one, I've probably spent hours trying different part arrangements too.
That trip from FranLab is genius!
I thought so too. "Frustration-free packaging!"
I once had shorts between GND and VCC on 2 boards (out of the 5). Now, I always do a continuity test between my power rails. Go figure!
Uh.... On a retro board from my gerbers?? Did you un-select "individually tested"? Or maybe your board house does not test them by default?
@@JohnsBasement No, it was my own boards (6502 SBC rev 4). But that's a fair point, I'm not sure I unselected "individually testes". I'll be more vigilant next time. As for the board house, it's JLCPCB... I usually don't have any issues with them.
I've followed Fran Lab for some time and glad I came across this channel. I always wanted to build a retro Z80 system
and after watching a of the videos I may do some redesigns adding in a SD card. I don't know if its possible but I wonder
if I couldn't use one of the SIO serial chips channel to interface to the SD card. Since the SIO can work in a synchronous
mode would speed up access time and less CPU overhead. Just an idea.
I wondered about that too. It might be possible if you can accurately control the clock in relation to the SSEL signal.
Please let me know if you can find a simple solution!
I am looking at building a multi-IO board to speed it up with a hardware SPI SD interface as well as other things like joysticks, keyboard and a graphic display.
Hey John, for the next rev, how about adding an ftdi header (maybe below the printer header) that would make the max232 and capacitors optional as well right? How much power does the board require to run? Might be possible to power it from the ftdi as well....
The next project might just have a USB adapter on board.
I ended up putting the ground plane on the back layer, and the power plane on the front layer on my two-layer projects. My thinking would be the same if I did 4-layer boards, as there would be more contact with the pads on the top layer for the power plane. Inner layers would be ground planes, of course. Do you see any issues with this method?
The issue would be that you won't have access to signals for testing.
Dave Jones recorded a piece on this exact issue: th-cam.com/video/2v5IvaWrPKk/w-d-xo.html But he got sidetracked on some DRC errors and I can not find the next in the series.
I am always amazed when I check the current carrying capacity of a via. You may ne need to worry about that so much for one chip. If you do want more, you can always add some vias near them to increase the cross-sectional area of copper that connects to the inner planes.
@@JohnsBasement Oh, I see what you mean. Now I under stand why having the power plane and copper plane in the inner layers would be more practical.
Hi John, real nice design and very well document, with regard to the bank selection chip U6 - 74HC374would the SN74xxx990 not be a nice alternative as this one would have readback of data is pin 1 was route to decoder ?
Yes. It would improve the efficiency of solving a race condition where an IRQ handler has to change the bank select.
But I'm not sure if a supply of dip versions are available at a reasonable price. 😕
@@JohnsBasement You right these would be hard to find @ reasonable prices, allow me to suggest an affordable alternative being a gal 16v8, I know it's against your design principle for this board but ... 😉
@@paulvanderwielen8173 Perhaps. But I find it tough to settle for a GAL when a low-end FPGA is waiting in the wings.
@@JohnsBasement Probably for a valid choice for a next rev board, thanks.
About the 40-pin breakout header... You put A8 to A15 in, but essentially, those will never be used again, since the retro board has all the memory one might need. We would only need A0 to A7 for IOs, won't we? Unless there's something I'm not understanding.
For my board, I'd probably replace A8 to A15 with IRQ0 to IRQ7 and put a 75HC148 interrupt priority encoder, and run interrupts in mode 1. What are your thoughts on that?
Well, some of the I/O instructions can use A8-A15... but if you are not using that feature then you are right.
If you are going to include the CTC and SIO then you are likely to prefer using mode 2 interrupts... and in that case you will want to include one end of the IRQ priority daisy chain.
In recent months, I have been thinking about doing a project with the Z8S180. Have a look. That SOC might throw a whole bunch of new ideas into the mix too. (Note, specifically, that I am not talking about the EZ80... that is a completely different thing.)
@@JohnsBasement Oh, I didn't realize that some IO instructions could use the upper address bits. Can you give an example? Since it's the case, I won't remove them from my header.
Is it possible to use both mode 1 and mode 2 interrupts at the same time? Meaning, can I use SIO PIO CTC, alongside non-Zilog chips, like the VDP?
@@microhobbyist outi, otir,... I'm sure not all would agree, but if you don't need that feature then it'd not be a crime to leave off the 8 MSBs.
Only one IRQ mode at any time can be used.
I can only wonder how that would look if it were wire-wrapped instead of using a PCB.
I don't suppose your software can render that automatically?
No. It can't as far as I know.
I suspect that at 10mhz, it would work because I've wire wrapped a few 68000 projects over the years that I think ran at 10.
R1,R2,R3 connect from U6 to the SD card MOSI/CLK/SSEL. My mini-resistor kit doesn't include 2.7K, but I have 2.2K and 3K. Would either of those work instead of 2.7K?
You mean R1, R3 and R5?
Since those resistors are part of a voltage divider, the voltage will go HIGHER as the size of R1, R2, and R3, are reduced. The max voltage for the SD signals is 3.3V! Using 2.2K will probably be OK. But don;t make them any smaller.
2.2K paired with 4.7K will make the theoretical high voltage 3.4V. But it is not too bad.
3K paired with 4.7 will make the theoretical high voltage 3.05V. That is a bit low. But it is likely to work OK.
The math for SD_MOSI works like this:
SD_MOSI max voltage = 5V * R2/(R2+R1)
As drawn:
R2=4.7K
R1=2.7K
5 * 4.7/(4.7+2.7) = 3.175V
If we substitute 3K or 2.2K:
5 * 4.7/(4.7+3) = 3.051V
5 * 4.7/(4.7+2.2) = 3.405V
You can change both R1 and R2 as needed. Make sure your total resistance stays between 4K and 8K or so.
@@JohnsBasement Thank you! That's very helpful.
Would the same logic apply to the programmer board, where there are the 2K7 resistors?
@@joelburton5509 The 2.7K parts on the programmer are all nominal. Anything from 2K-5K should be fine.
Can you use Z8400 as a replacement for the Z80?
I am not SURE. But I suspect it would.
Potential problems are that 1) the clock oscillator overshoots more than I'd like it to (In a rev 4 design, I will add a series resistor to the outputs of X1 and X2) and 2) the output drive voltage on the Z8400 is spec'd lower than that on the Z84C00 that I used on my board.
I'd try it and see. (Please let us know how it goes!) I wouldn't expect anything to get physically damaged if it doesn't work. So you could just swap the CPU out if that happens.
If you REALLY wanted to hid the SD card for a retro look, you could have tried to put THAT on the back side of the board too! 10:55, looks like a rev 4 in the works!
True. Ofcourse with an otherwise thru-hole board, i am lacking options! 😕
And yes, there will be a Rev 4 at some point. Rev 3 has been running CP/M 2.2 fine for me for weeks. Improvements could be made, however, it is not clear that they are necessary.
See the 'issues' list on the github project page. I have been documenting my thoughts there.
How important is the bonding option on the Z80 SIO? Your design uses SIO/0. Toying with the idea of an SMD version of this circuit (emphasis on 'toying'), I discoverd that there does not seem to be an SMD version of SIO/0, only /2, /3. /4. Does such a lack of SIO/0 make an SMD version impossible or at least more problematic? Maybe there other such problems lurking in the dark making an SMD version impossible? Or maybe this is just a dumb idea?
You'll have to define 'dumb.'
I am mulling over a next generation surface mount Z80 board. We should talk if you think there is something that we could collaborate on... even if only to do some design reviews.
I am looking at using a Z8S18020FSG. It is a SOC with a 20MHz Z80, 16-bit counters, two UARTs, and an MMU that is a bit nicer than the one I have on my Retro board. This should free up enough space on a 100x100mm board for an FPGA that can emit VGA video and do other gate-hungry things as well.
@@JohnsBasement Why not Z84C0010VEG (44 PLCC) versus Z8S18020FSG (80 QFP)? The later has 12 NC pins that are omitted on the former. Makes for easier soldering unless you are planning pick and place of components - which I doubt knowing you as the Mr. Frugal that you seem to be. 🙂
@@DavidTLutz when youtube generates enough to cover one of my hobby projects, I'll up the ante!
Meanwhile... Who stocks the VEG package??
I've got a LQFP in stock that I don't have trouble soldering in. I got others asking to go surface mount too.. so I thought I would on the next version... Plus I have to anyway if I want to take a swing at creating a VGA video controller in a FPGA... Which has been on my TODO list since I started my Retro project.
@@JohnsBasement Oh, so you are farther along than I realized - I took "looking" (above) to mean you had not yet decided. Digikey stocks the Z84C0010VEG. However, it is only 10 MHz but still 5V. It is cheaper then the Z8S18020FSG. FPGA and VGA - are you aware of Haskell and Hanna's book? Amazon: Advanced Digital Design Using Digilent FPGA Boards: VHDL / VGA Graphics Examples.
@@DavidTLutz Nothing is cast in stone until all the parts are soldered on... and even then... there is usually a Rev 2 ;-)
That book title is new to me. I got my toehold from Pong Chu's book: a.co/d/hjYOGjc
I try to aim for hobby things that the students on my FRC team could afford ($$) to do if they were so inclined to try. To that end I have been trying to stick to hand-solderable parts that have software tools that are easy to deal with over the course of time.
Re-installing the giant IDEs from the big vendors every time someone decides to change the color of some rand-o menu buttons is getting really annoying.
If it can fit onto a ICE40HX4K, then I'd like to do so and build on what I was doing in these projects:
github.com/johnwinans/IceStick-Examples
github.com/johnwinans/2057-ICE40HX4K-TQ144-breakout
github.com/johnwinans/2060-ORIO2
github.com/johnwinans/ORIO2-software
The IceStick example tool install is getting stale... but that series of tools is surprisingly light weight and easy to learn how to use.
It should be easy to pop one next to a Z8S180 and implement a VGA display. What is unknown to me at the moment is how fancy it can get. I know that 1024x768 is doable without even adding any extra RAM (because I already did it on the 2057 breakout board) and I expect that I could make sprites work too. The unknowns will reveal themselves when it comes to how much video memory I can include and how it should be accessed from the Z80.
THIS is why I have been playing with the TMS9118! Before I commit to my first-gen architecture, I wanted to see how cumbersome it is to use a system with none of its VRAM directly mapped into the CPU address space.
Probably include PWM audio, PS2 keyboard/mouse, SNES game controller ports (original/non-USB), etc.