CTS_S1_L1: Clock Tree Synthesis Introduction (Part 1)

Clock Tree synthesis is very important in PD FLow. Understanding of that's also very important.
In this lecture, we are going to discuss why we usually do CTS? What are the challanges during connecting clock source pin to clock of Flipflop?
Below are links of previous Lecture series which will help you to jump directly to understand some concepts.
CLK_L1: Clock Skew Introduction (Part 1 ) • CLK_L1 - Clock Skew In...
CLK_L2: Clock Skew Introduction (Part 2 )
CLK_L3: Importance of Clock Skew in Timing Analysis (Part1) • CLK_L3 -Importance of ...
CLK_L4: Importance of Clock Skew in Timing Analysis (Part2) • CLK_L4 - Importance of...
CLK_L5: Clock Skew and Hold Violation • CLK_L5 - Clock Skew an...
CLK_L6: Clock Skew and Setup Violation • CLK_L6 - Clock Skew an...
CLK_L7: Challange in Fixing Setup and Hold Violation Using Clock Skew (Part 1) • CLK_L7- Challange in ...
CLK_L8: Challange in Fixing Setup and Hold Violation Using Clock Skew (Part 2) • CLK_L8- Challange in F...
CLK_L9:Fixing Large No of Hold Violation using Clock Skew (Part1) • CLK_L9 - Fixing Large ...
CLK_L10: Fixing Large No of Hold Violation using Clock Skew (Part2) • CLK_L10 - Fixing Large...

[@rahulchanana8151]

The amount of hardwork you are putting in preparing this lectures is really appreciable....very nicely explained...Thank you so much sir👍👍

[@k.nagendra507]

I want c continue to next class sir

[@husainsayed0007]

Please continue to upload videos..

[@meandersoul]

Sir please upload next lectures of Cts. Thank you.

[@StayInBliss]

You are great helps to us sir

[@kumar2501]

Awesome sir

[@ramamurthy7937]

hi sir,
your explanation is awesome please explain the concept in an easy way, without taking more flipflops, so that it will be esay for all to understand other things are perfect

[@kdeepakkartik]

Hi Sir, it was a nice video, could you please post your next continuing video.

[@mohdsalmankhan9733]

Hi sir,
It was really a nice video explaining everything in sequence.
Can we hope to get next video lesson of this series?

[@niycxplay]

sir do you have the part2?

[@harshvardhanupadhyay9920]

sir, kindly upload next lecture of it..!!

[@vishnuvardanreddy9618]

Which drive strength buffers used for building clk tree and y

[@anandhavaldar1992]

Please upload next videos

[@gayathrilasyamarkapuram2160]

really nice sir.. can u please the information provide the information regarding what are the challenges that we encounter in placement and routing . what are the rules should follow for macro placement..

[@saivijayabhaskargade1528]

thanq so much sir....

[@vinaykumarvinni3007]

I think we can do high fanout net synthesis method to avoid the problem

[@karanaggarwal1905]

Sir when will u release it's next video

[@venkatasriram2066]

Sir... Giving multiple clock inputs may avoid the problem

[@prasadgadipalli7077]

When will be part 2

[@karanaggarwal1905]

Sir when will u release it's next video y

[@vlsiexpert]

Karan Aggarwal some time end of next week

[@karanaggarwal1905]

VLSI EXPERT thank u sir

[@karanaggarwal1905]

VLSI EXPERT can u suggest something from where should I study placement and power routing ?

[@AmitGupta-zu8yd]

@@vlsiexpert how do we get further more videos of yours sir? It's been a while you haven't uploaded anything regarding CTS..