SPARC Version 9, lecture by David Ditzel

SPARC Version 9: Adding 64-Bit Addressing and Robustness to an Existing RISC Architecture, lecture by David Ditzel. The video was recorded in September 1992.
From University Video Communications' catalog:
"SPARC started as a 32-bit RISC (reduced instruction set architecture). This talk describes the evolution of SPARC to a full 64-bit architecture, and the design decisions that drove those changes. In addition to extending the address range, a number of changes were made to better support compilers, operating systems, superscalar implementations, context switching, and fault tolerant systems."
Lot number: X6636.2013
Catalog Number: 102624695

[@LMB222]

What an inspiring, captivating… 30 year old sales video!

[@opensparcbox]

IMO the best overview/intro of improvements made with the SPARC V9 ISA. Now I will take a closer look into the SPARC Architecture Manual V9 for more details. - Thanks for sharing.

[@RishabhRaja01]

Thanks a lot David for this explanation. :)

[@epakai]

"So because of that I think it's very unlikely that [Intel x86] in the long run will ever catch up to where the RISC architectures are." Dave later went on to found Transmeta, a producer of VLIW cores that ran x86 code. x86 has spent quite a while in the lead since then.

[@0LoneTech]

And if you listen to the sentence before, "that" refers to how x86 was register starved, a deficiency adjusted by AMD's x86-64. x86 never did catch up, and the modern x86-compatible processors caught up exactly the way he described.

[@LMB222]

​@@0LoneTechand generally, with AMD64 we've got practically a new architecture that only provides - thankfully - limited backwards compatibility with 32 and 16 bit modes. About time!
Does 16 bit protected mode even run on AMD64?

[@0LoneTech]

@@LMB222 IIRC it does not; you can use dosbox but not dosemu.

[@KabelkowyJoe]

41:00 x86-64 you can do whatever you want, specify old register and you are ready to go, way SPARC did that was better for them, they could keep architecture simpler, harder to "user"

[@KabelkowyJoe]

12:00 SO AMD - Jim Keeler did it better? You can run code in 2 modes 32 and 64, rest like CMOV we take for granted in x86 but was introduced in Pentium 166MHz ~1995 32:00 CMPXCHG there are new version of this instruction introduced in Core Duo and Athlon 64 on AM2 platform required to run Windows 10. Lecture about DEC Alhpa was much more impressive. Forgot name of designer. It was 1992 but it seems like Sparc architecture was designed to be cheap and simple. All these RISC architectures can define 3 arguments to instructions. 2x sources and 1 destination. Separates load, store from operation. This is why zero register is needed. Plus in 1992 RISC needed pipeline like fish needs water CISC allows you to initially solve that, tweak by more complex logic to run your sophisticated instructions in 1 cycle without need to pipeline that. Pipeline require good branch prediction right from start, and strict cooperation between compiler and architecture. Much easier to make pipeline if your instructions are already simple and can easly run 1 cycle. But forces user to sacrifice makes it harder to write code.
Variable lenght instruction opcodes was requirement to keep backward compatbility, but it adds to complexity of decoder.. tradeofs so called CISC. On other hand allowed to make dozen of enhancements to instruction set. Also AGU on Intel is much more sophisticated. Not breaking backward compatbility. SPARC could not make client happeier by introduction of new instructions.

[@KabelkowyJoe]

Oh end SCAZ REPZ on x86 allows very very quick memory copy 1 cycle for 32bit data,

[@KabelkowyJoe]

43:00 And then shit happened - Intel introduced superscalar Pentium, internally RISC with "architecture" up front to the "client" in CISC, form of ROM - microcode, best of both worlds. Then Pentium II multiple execution units to say bye bye to everyone else. Then Pentium III 1.2GHz - prefetch. Then Core? Out of order execution, then Core 2 Duo borrowed from Pentium 4 uops cache, translating "client" to world of internal RISC and keeping results for future use. ZEN did the same. Plus improved memory subsystem to be ~45nm instead of 100ns - access time to memory cache miss was of old 368 100ns :)
Good thing about RISC "centric" architecture is that it remain small, and can be optimized in software. But it's not ideal - from user's perspective. That extra translation adds to flexability of us - users, makes assembly language easier. But same code wont run same on every processor. What is funny is that RISC is best for embedded, to keep simple and low power. Same time makes it harder for programer if you dare to write in assembly. Nobody write in assembly anymore but if you dare RISC makes it way more complicated.

[@lawrencemanning]

All very insightful and interesting except the last part. CISC ISAs typically show very little orthogonality, which is why RISC ISAs are generally much nicer to program for.