Hi sir, I want to know if the CNTFET can be used for low-frequency applications, if so what are the parameters that effects to control of the frequency of CNTFET
In your NCNTL3 vams file there are four port (drain gate source sub) but when you make a symbol its showing 5 pin one "couplenode" is there ,can you tell me the reason??
Sir TFET model library files are not available as CNFET can you help me like will it be available or do we need to design in TFET in tcad and extract parameters and then load into cadence??
hello sir this video is really great it was very helpfull for me. but when i did power analysis its coming 0 for total power. the circuit i was using it was a gated SRAM.
Sir this is very nice and elaborative video..I have one doubt,if I have to compare performance of 22nm cmos technology with cntfet,then is it enough to just change length of cnt and length of S/D in cntfet as 22nm,other parameters in Standford university model (which is given for 32nm) remains same?
Yes changing length of cnt and length of S/D in cntfet as 22nm is good enough. You can use a single tube for CNFET ( specify it in your writeup) and use miminum permitted channel width of MOSFET ( specifu the channel width)
sir while simulating the designs with these models, getting power signal as zero output at every instance it is showing zero only. i tried for several designs and i am getting the same power signal as zero signal. and while creating this cntfet library i didn't add it to existing libraries like gpdk45 or something else. i got the functionality of the designs correct but the power signal as zero. kindly response as soon as possible sir. thank you sir
You will have to plot the current from VDD (Power supply) take average and multiply with VDD. You may listen to my video th-cam.com/video/bf5cCtLoYTo/w-d-xo.html for the procedure to compute power.
@@SanjayVidhyadharan this product of Iavg and VDD is the static power right sir can you please tell how to calculte the dynamic power for cntfet models
GAA is gate all around ( gate on all sides of channel). We do have GAA TFETSs and GAA CNFET but not all CNTFETs and TFETS have GAA structure . FINFETs have gate on three sides , with SOI at the bottom.
Sir, I am getting power in negative value after plotting the current from VDD (Power supply) take average and multiply with VDD. what could be the reason sir?
It will be negative as power dissipated in the source is negative. The source has given power to the circuit. The components in the circuit will have positive power.
The model also includes a gate interconnect parasitic capacitance Cgtg which is about 110 aF/μm for one side. You may neglect it an keep is open for schematic simulations.
Hi, can you please explain why in the object properties of the NCNFET you do not see the 'tubes' parameter in the CDF Parameter of view for veriloga.
Not sure why you arenot seeing tubes as a pararmeter
Hi sir, I want to know if the CNTFET can be used for low-frequency applications, if so what are the parameters that effects to control of the frequency of CNTFET
Yes, you can.
Sir I'm getting any error like this - "error when elaborating the instance NCNFET_L1. Simulation must be terminated"
Mail me the deatails with snapshots sanjay.vidhyadharan@pilani.bits-pilani.ac.in
Thank you so much for this awesome presentation.
My pleasure
In your NCNTL3 vams file there are four port (drain gate source sub) but when you make a symbol its showing 5 pin one "couplenode" is there ,can you tell me the reason??
You can ground the couple node. Couple node comes from NCNTL1 vams which is invokde in L3.
sir..where to get the gpdk45?mine only got gpdk090
You need to buy the files from Candence. Alternativly yo can use PTM models. th-cam.com/video/RRcyEBu9Z0M/w-d-xo.html
For 90nm its showing fatel error what to alter in the verilog code
you mat mail me the error details. I will have a look
Sir TFET model library files are not available as CNFET can you help me like will it be available or do we need to design in TFET in tcad and extract parameters and then load into cadence??
TFET model files are avliable
nanohub.org/publications/31/1
www.ndcl.ee.psu.edu/downloads.asp
From where do I download and install Cadence tools such as virtuoso 6.1.x with license ?
It is not available for free. You need to buy it
@@SanjayVidhyadharan AFAIk, these tools are not available for individuals to buy. Only universities and companies can buy
hello sir this video is really great it was very helpfull for me. but when i did power analysis its coming 0 for total power. the circuit i was using it was a gated SRAM.
Yes, this model will not compute power. You need to plot current from power supplt source , take average and multiply with VDD to get power.
Thanks so much for you guys again 😊
My pleasure 😊
Sir this is very nice and elaborative video..I have one doubt,if I have to compare performance of 22nm cmos technology with cntfet,then is it enough to just change length of cnt and length of S/D in cntfet as 22nm,other parameters in Standford university model (which is given for 32nm) remains same?
Yes changing length of cnt and length of S/D in cntfet as 22nm is good enough. You can use a single tube for CNFET ( specify it in your writeup) and use miminum permitted channel width of MOSFET ( specifu the channel width)
Nice to know that it is of help.
sir while simulating the designs with these models, getting power signal as zero output at every instance it is showing zero only. i tried for several designs and i am getting the same power signal as zero signal. and while creating this cntfet library i didn't add it to existing libraries like gpdk45 or something else.
i got the functionality of the designs correct but the power signal as zero. kindly response as soon as possible sir.
thank you sir
You will have to plot the current from VDD (Power supply) take average and multiply with VDD. You may listen to my video th-cam.com/video/bf5cCtLoYTo/w-d-xo.html for the procedure to compute power.
@@SanjayVidhyadharan thank you sir
I will do it, if I got any errors, I inform you sir, please rectify it
@@SanjayVidhyadharan this product of Iavg and VDD is the static power right sir
can you please tell how to calculte the dynamic power for cntfet models
Sir, what's difference between GAA device and CNFET device?
GAA is gate all around ( gate on all sides of channel). We do have GAA TFETSs and GAA CNFET but not all CNTFETs and TFETS have GAA structure . FINFETs have gate on three sides , with SOI at the bottom.
@@SanjayVidhyadharan very interesting!
Thanks 👍
Sir, I am getting power in negative value after plotting the current from VDD (Power supply) take average and multiply with VDD. what could be the reason sir?
It will be negative as power dissipated in the source is negative. The source has given power to the circuit. The components in the circuit will have positive power.
@@SanjayVidhyadharan Thankyou sir. for some circuits Average power is becoming zero?? What could be the cause sir?
Can we do GNRFET using this cadence and verilog sir
If we have the SPICE model we can import it
Sir can you do a vedio on how to import GNRFET MODEL into cadence sir
The proceddure may be similar. I have not tried it
thank you sir, what is the use of coupleNode sir
The model also includes a gate interconnect parasitic capacitance Cgtg which is about 110 aF/μm for one side. You may neglect it an keep is open for schematic simulations.
Sir How to draw the layout using CNTFET Model for a circuit?
Layout is not possible. You can try stick diagram to get rough estimate of area.
@@SanjayVidhyadharan Thank You Sir
sir, how to put all the .va file into linux server?
Could you please elaborate you problem. You may mail me the details.
how to tackle Spectre related errors sir?
Can you mail; me the details. sanjayv@hyderabad.bits-pilani.ac.in
Nice Explanation sir
Thankyou
Can we import cntfet in ltspice?
I have not tried yet in LT SPICE. I have explained how to import CNFET model into cadence. th-cam.com/video/jhZuzXzgPcc/w-d-xo.html
sir, how to download 45nm technology file?
sanjayvidhyadharan.in/blog/digital-vlsi/
Lecture-3
@@SanjayVidhyadharan Sir, i am not getting all those object parameters to edit. Can you please help.
CAN YOU SHARE YOUR DESIGN FILES
The model file are valiable in standford university web page.
Thank you very much sir
Most welcome