Love this project. Looking forward to seeing it in operation. Why can't you send out a paired signal, one which is as you have here, and the other explicitly crafted to compensate for the peculiarities of other wave, so you can send slightly offsetting voltages to add to the mix so the square wave can be crafted into a true square wave?
That's an interesting idea but honestly I have no idea how to craft such a waveform. And it would surely depend on the position of each card, and I would definitely want to avoid a different circuit for each card.
Maybe an 8x clock driving the second line, with some switching circuitry to send out -nV only at certain points on the cycle, 0v everywhere else. A logical TICK-tock for the main clock (T would be rising edge, t would be the falling edge), with a +0.3V on the T, and a -0.3V on the t. The voltages get netted together at each point, resulting in a more square square wave. Just a thought. You could also trigger the second signal off the rising and falling edges of the clock for the first. No idea if it would work, but it seems logical.
That "megabus" thing looks more and more problematic. Maybe it's a good time to rethink the architecture a little bit. Like, for example, split those 32 registers into groups, with 4 (8?) registers per. And hide each group behind a buffer.
You might still have the power problem: the load is still 50 Ohm, even if for high frequency components only. But you're toggling at 20 MHz... After connecting lots of cards it will be worse. Have you measured the power consumption? What about when two strips connected (to buffer's separate outputs)?
Yes, that is going to be fun. In chapter 1 we learned that the card has 3 inputs on a destination bit. That is, the register file is going to present 9pF per card on the destination bus. For 31 cards, that is 279pF on the desination bus purely from the register file. 64mA per pin will still change the bus in 14ns, but the worst case current is 2A. On each source bus there will be 32 9pF outputs in the register file, or 288pF, about the same as on the input. So if we guesstimate 50% toggling signals per 50ns, that's around 0.8A in the capacitive loads. Not too terrible, considering that all-ones in the registers is going to consume another 1.2A in LED current. It might be a good experiment to load all 32 bits on a source bus with the expected 288pF and see if the register performs correctly. This is a nasty sharp-edged current pulse.
Yep, the capacitance is a worry. Note that each output, if I use a buffer, is limited to 50mA, so with say 300pF, it would take 12ns to go from 0v to 2v (the logic 1 threshold). Actually, I'll be using a 74LVT16374, so it's 64mA going high, and 32mA going low. Let's just say that's 50mA on either side. The transition speed is okay, since the input of the 74LVT16374 needs to be faster than 10ns/V, and this will be doing 6ns/V. Now, worst case, all 32 bits toggle, requiring 1.6A for 12ns. There are four VCC pins per chip, and each maxes out at 64mA. But I don't know if that's specified as continuous or not. I know that plenty of CMOS chips do multiple amps over a few nanoseconds just to switch. We'll just have to see. This is what decoupling (or charge reservoir) capacitors are for -- to provide that bit of ooomph to do the switching. Also, the input capacitance of a '16374 is 4pF, so it's not as bad as a '244 buffer. That's a total of say 130pF, so the delay is even less. I think it's worth a try!
Guesstimate of decoupling capacitor: 400mA per VCC pin for 6ns (remember the capacitance is 130pF, a little less than half), and if I don't want VCC to dip more than say 0.2 V, I get 12nF. Considering that most decoupling capacitors are 100nF, I'd say we don't have to worry too much. I hope.
Argh, wait, I will actually want to use a buffer as the input for each card, otherwise I have three inputs per card, not one. And without the buffer, each line has to travel a lot further on the card itself, which messes up the transmission characteristics. So, buffer.
Yes, a buffer will reduce the capacitive load on the destination bus by 3x, but if you go that route, are you not back to a design with a single register, leds on the output of the register, and tristate buffers for driving the source busses? It does have advantages, but means you will need to order a new pile of register cards. If you are redoing the register cards, would it be an idea to include decoding on each register card? It probably costs a bit since there will be many copies, but could reduce the 96? select wires you will otherwise need for the register bank, and possibly eliminate a register addressing card.
loving this project!! by the way, it looks like your outro got messed up somehow so that it jumps through at very high framerate to the point where it says "and I can't sing". It might not matter, but if you care, now you know.
Love this project. Looking forward to seeing it in operation.
Why can't you send out a paired signal, one which is as you have here, and the other explicitly crafted to compensate for the peculiarities of other wave, so you can send slightly offsetting voltages to add to the mix so the square wave can be crafted into a true square wave?
That's an interesting idea but honestly I have no idea how to craft such a waveform. And it would surely depend on the position of each card, and I would definitely want to avoid a different circuit for each card.
Maybe an 8x clock driving the second line, with some switching circuitry to send out -nV only at certain points on the cycle, 0v everywhere else. A logical TICK-tock for the main clock (T would be rising edge, t would be the falling edge), with a +0.3V on the T, and a -0.3V on the t. The voltages get netted together at each point, resulting in a more square square wave.
Just a thought. You could also trigger the second signal off the rising and falling edges of the clock for the first.
No idea if it would work, but it seems logical.
That "megabus" thing looks more and more problematic. Maybe it's a good time to rethink the architecture a little bit. Like, for example, split those 32 registers into groups, with 4 (8?) registers per. And hide each group behind a buffer.
You might still have the power problem: the load is still 50 Ohm, even if for high frequency components only. But you're toggling at 20 MHz... After connecting lots of cards it will be worse.
Have you measured the power consumption? What about when two strips connected (to buffer's separate outputs)?
Yes, that is going to be fun. In chapter 1 we learned that the card has 3 inputs on a destination bit. That is, the register file is going to present 9pF per card on the destination bus. For 31 cards, that is 279pF on the desination bus purely from the register file. 64mA per pin will still change the bus in 14ns, but the worst case current is 2A.
On each source bus there will be 32 9pF outputs in the register file, or 288pF, about the same as on the input.
So if we guesstimate 50% toggling signals per 50ns, that's around 0.8A in the capacitive loads. Not too terrible, considering that all-ones in the registers is going to consume another 1.2A in LED current.
It might be a good experiment to load all 32 bits on a source bus with the expected 288pF and see if the register performs correctly. This is a nasty sharp-edged current pulse.
Yep, the capacitance is a worry. Note that each output, if I use a buffer, is limited to 50mA, so with say 300pF, it would take 12ns to go from 0v to 2v (the logic 1 threshold). Actually, I'll be using a 74LVT16374, so it's 64mA going high, and 32mA going low. Let's just say that's 50mA on either side. The transition speed is okay, since the input of the 74LVT16374 needs to be faster than 10ns/V, and this will be doing 6ns/V.
Now, worst case, all 32 bits toggle, requiring 1.6A for 12ns. There are four VCC pins per chip, and each maxes out at 64mA. But I don't know if that's specified as continuous or not. I know that plenty of CMOS chips do multiple amps over a few nanoseconds just to switch. We'll just have to see. This is what decoupling (or charge reservoir) capacitors are for -- to provide that bit of ooomph to do the switching.
Also, the input capacitance of a '16374 is 4pF, so it's not as bad as a '244 buffer. That's a total of say 130pF, so the delay is even less.
I think it's worth a try!
Guesstimate of decoupling capacitor: 400mA per VCC pin for 6ns (remember the capacitance is 130pF, a little less than half), and if I don't want VCC to dip more than say 0.2 V, I get 12nF. Considering that most decoupling capacitors are 100nF, I'd say we don't have to worry too much. I hope.
Argh, wait, I will actually want to use a buffer as the input for each card, otherwise I have three inputs per card, not one. And without the buffer, each line has to travel a lot further on the card itself, which messes up the transmission characteristics. So, buffer.
Yes, a buffer will reduce the capacitive load on the destination bus by 3x, but if you go that route, are you not back to a design with a single register, leds on the output of the register, and tristate buffers for driving the source busses? It does have advantages, but means you will need to order a new pile of register cards.
If you are redoing the register cards, would it be an idea to include decoding on each register card? It probably costs a bit since there will be many copies, but could reduce the 96? select wires you will otherwise need for the register bank, and possibly eliminate a register addressing card.
loving this project!! by the way, it looks like your outro got messed up somehow so that it jumps through at very high framerate to the point where it says "and I can't sing". It might not matter, but if you care, now you know.
It was a joke. At the beginning he played first half of the intro and in the end last half. Because it's short episode I guess.
I rather think it's deliberate, given that this is just a quick update and the intro was also abbreviated.
Gotcha, just looked broken, that's all
Yep, it was a joke. Well, some jokes work, some not so much :)
It worked. My wife and son love your intro. They both sing it when it comes on.